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71. 发明授权

US09552865B2 Method and apparatus for calibrating write timing in a memory system 有权
标题翻译：用于校准存储器系统中的写入定时的方法和装置
公开(公告)号：US09552865B2
公开(公告)日：2017-01-24
申请号：US14931513
申请日：2015-11-03
申请人： Rambus Inc.
发明人： Thomas J. Giovannini , Alok Gupta , Ian Shaeffer , Steven C. Woo
IPC分类号： G11C11/4076 , G06F3/06 , G06F5/06 , G06F1/08 , G11C7/10 , G06F13/16 , G06F12/06 , G11C11/409 , G11C11/4096
CPC分类号： G11C11/4076 , G06F1/08 , G06F3/0629 , G06F3/0634 , G06F5/06 , G06F12/0646 , G06F13/1689 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/409 , G11C11/4096 , G11C2207/2254
摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
摘要翻译：描述了校准执行写操作所涉及的信号之间的时序关系的系统。该系统包括耦合到一组存储器芯片的存储器控制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系一个写操作。此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在相对于时钟信号的数据选通信号乘以时钟周期的倍数。

72. 发明授权

US09529602B1 Systems and methods for internet recovery and service 有权
标题翻译：互联网恢复和服务的系统和方法
公开(公告)号：US09529602B1
公开(公告)日：2016-12-27
申请号：US14805670
申请日：2015-07-22
申请人： Dell Products, L.P.
发明人： Todd Erick Swierk , Carlton A. Andrews , Yuan-Chang Lo , Philip M. Seibert , Mario Anthony Limonciello
IPC分类号： G06F9/24 , G06F15/177 , G06F9/44 , G06F9/445 , G06F3/06 , G06F21/57 , G06F9/50 , G06F12/06
CPC分类号： G06F9/441 , G06F3/0632 , G06F8/61 , G06F8/65 , G06F8/71 , G06F9/4401 , G06F9/4411 , G06F9/45558 , G06F9/5005 , G06F11/00 , G06F11/0706 , G06F11/0793 , G06F12/0646 , G06F21/57 , G06F21/575 , G06F2009/45579 , G06F2221/2141
摘要： Systems and methods for Internet recovery and service. In some embodiments, an Information Handling System (IHS) may comprise a processor and a Basic I/O System (BIOS) coupled to the processor, the BIOS having program instructions stored thereon that, upon execution by the processor, cause the IHS to: transmit a request to a backend server for a service Operating System (OS), where the request includes an identification (ID) of the IHS that enables the backend server to select two or more of a plurality of service OS components; receive the selected service OS components over a network; assemble the selected service OS components into the service OS; and boot the service OS.
摘要翻译：互联网恢复和服务的系统和方法。在一些实施例中，信息处理系统（IHS）可以包括耦合到处理器的处理器和基本I / O系统（BIOS），所述BIOS具有存储在其上的程序指令，其在由处理器执行时使得IHS：向服务操作系统（OS）的后端服务器发送请求，其中请求包括使得后端服务器能够选择多个服务OS组件中的两个或更多个的IHS的标识（ID）; 通过网络接收所选择的服务OS组件; 将所选择的服务OS组件组合到服务OS中; 并启动服务操作系统。

73. 发明申请

US20160357459A1 VIRTUAL GROUPING OF MEMORY 有权
公开(公告)号：US20160357459A1
公开(公告)日：2016-12-08
申请号：US15244010
申请日：2016-08-23
申请人： International Business Machines Corporation
发明人： Timothy J. Dell , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0664 , G06F3/0683 , G06F12/0646 , G06F12/0661 , G06F2212/1024 , G06F2212/152
摘要： The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.

74. 发明申请

US20160350236A1 MEMORY SWAP FOR DIRECT MEMORY ACCESS BY A DEVICE ASSIGNED TO A GUEST OPERATING SYSTEM 有权
标题翻译：由分配给客户操作系统的设备进行直接存储器访问的存储器切换
公开(公告)号：US20160350236A1
公开(公告)日：2016-12-01
申请号：US14724318
申请日：2015-05-28
申请人： Red Hat Israel, Ltd.
发明人： Michael Tsirkin , Andrea Arcangeli
IPC分类号： G06F12/10 , G06F9/455 , G06F12/06 , G06F3/06
CPC分类号： G06F12/1081 , G06F3/0604 , G06F3/061 , G06F3/0638 , G06F3/0673 , G06F9/45558 , G06F11/00 , G06F12/0646 , G06F13/28 , G06F2009/45579 , G06F2009/45583 , G06F2212/1016 , G06F2212/65
摘要： A hypervisor detects a page fault associated with the request for a device assigned to a guest operating system to perform direct memory access (DMA) of a requested page of memory, invalidates a mapping in a central processing unit (CPU) page table of a guest physical address to a host physical address for a candidate page for being swapped out of host memory, checks a DMA access state of the candidate page to determine whether or not the candidate page can be swapped out from the host memory, and removes the candidate page from the host memory in response to determining that the DMA access state indicates that the candidate page can be swapped out.
摘要翻译：虚拟机管理程序检测与分配给客户操作系统的设备的请求相关联的页面错误，以执行所请求的存储器页面的直接存储器访问（DMA），使访客的中央处理单元（CPU）页表中的映射无效物理地址到候选页面的主机物理地址，用于被转换出主机存储器，检查候选页面的DMA访问状态，以确定候选页面是否可以从主机存储器中换出，并且移除候选页面响应于确定DMA访问状态指示候选页面可以被换出，来自主机存储器。

75. 发明申请

US20160342342A1 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND DATA ACCESS METHOD 审中-公开
标题翻译：信息处理设备，信息处理系统和数据访问方法
公开(公告)号：US20160342342A1
公开(公告)日：2016-11-24
申请号：US15114612
申请日：2015-02-04
申请人： NEC CORPORATION
发明人： Masaki KAN , Jun SUZUKI , Yuki HAYASHI
IPC分类号： G06F3/06 , G06F12/06 , H04L12/707 , G06F17/30 , H04L29/08
CPC分类号： G06F3/0611 , G06F3/0644 , G06F3/067 , G06F12/0646 , G06F12/0802 , G06F16/2228 , G06F16/23 , G06F2212/1024 , G06F2212/1041 , G06F2212/154 , H04L45/22 , H04L67/1097
摘要： An information processing device is provided that improves the responsiveness of a storage system and a storage device that is accessed via a network. This information processing device includes: a means that calculates an address identifying an area, on the basis of an access identifier specifying data to be accessed, said area being in a storage device that stores a first data corresponding to the access identifier; and a means that obtains the first data included in second data being data for the area and read on the basis of the calculated address, on the basis of management information included in the second data, and executes a first data operation on the second data.
摘要翻译：提供了一种信息处理设备，其提高了经由网络访问的存储系统和存储设备的响应性。该信息处理装置包括：基于指定要访问的数据的访问标识符来计算识别区域的地址的装置，所述区域在存储与存取标识符对应的第一数据的存储装置中; 以及基于包含在第二数据中的管理信息，获得包含在第二数据中的作为该区域的数据并基于计算出的地址读取的第一数据的装置，并对第二数据执行第一数据操作。

76. 发明申请

US20160314080A1 APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA 有权
公开(公告)号：US20160314080A1
公开(公告)日：2016-10-27
申请号：US15202279
申请日：2016-07-05
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F12/128
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

77. 发明申请

US20160313774A1 MULTI-CORE FUSE DECOMPRESSION MECHANISM 有权
公开(公告)号：US20160313774A1
公开(公告)日：2016-10-27
申请号：US15202330
申请日：2016-07-05
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F1/24 , G06F12/0875 , G06F9/44
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

78. 发明授权

US09448930B2 Memory heaps in a memory model for a unified computing system 有权
公开(公告)号：US09448930B2
公开(公告)日：2016-09-20
申请号：US14833850
申请日：2015-08-24
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Anthony Asaro , Kevin Normoyle , Mark Hummel
IPC分类号： G06F12/02 , G06F12/08 , G06F12/06 , G06F12/10
CPC分类号： G06F12/1036 , G06F12/0284 , G06F12/0646 , G06F12/08 , G06F12/10 , G06F12/109 , G06F2212/1012 , G06F2212/152 , G06F2212/656 , G06F2212/657
摘要： A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

79. 发明授权

US09405485B2 Method and apparatus for writing data to a flash memory 有权
标题翻译：将数据写入闪速存储器的方法和装置
公开(公告)号：US09405485B2
公开(公告)日：2016-08-02
申请号：US14319990
申请日：2014-06-30
申请人： SILICONMOTION INC.
发明人： Chun-Kun Lee , Wei-Yi Hsiao
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02 , G06F12/06 , G06F12/08 , G06F13/16
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0679 , G06F3/0689 , G06F12/0246 , G06F12/0638 , G06F12/0646 , G06F12/0802 , G06F13/1673 , G06F2212/7203
摘要： The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.
摘要翻译：用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到外部缓冲区然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。

80. 发明申请

US20160210075A1 OBJECT MEMORY INSTRUCTION SET 审中-公开
标题翻译：对象存储器指令集
公开(公告)号：US20160210075A1
公开(公告)日：2016-07-21
申请号：US15001526
申请日：2016-01-20
申请人： ULTRATA LLC
发明人： STEVEN FRANK , LARRY REBACK
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0604 , G06F3/0613 , G06F3/0631 , G06F3/0632 , G06F3/0644 , G06F3/0647 , G06F3/065 , G06F3/0659 , G06F3/067 , G06F3/0673 , G06F3/0683 , G06F3/0685 , G06F12/0646 , G06F12/0824 , G06F12/0837 , G06F2212/2542 , H04L67/1097
摘要： Embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to define arbitrary, parallel functionality such as: direct object address manipulation and generation without the overhead of complex address translation and software layers to manage differing address space; direct object authentication with no runtime overhead that can be set based on secure 3rd party authentication software; object related memory computing in which, as objects move between nodes, the computing can move with them; and parallelism that is dynamically and transparent based on scale and activity. These instructions are divided into three conceptual classes: memory reference including load, store, and special memory fabric instructions; control flow including fork, join, and branches; and execute including arithmetic and comparison instructions.
摘要翻译：本发明的实施例涉及一种对象存储器结构的指令集。该对象存储器结构指令集可用于定义任意并行的功能，例如：直接对象地址处理和生成，无需复杂地址转换和软件层的开销来管理不同的地址空间; 直接对象认证，无需基于安全第三方认证软件设置的运行时开销; 对象相关的内存计算，其中当对象在节点之间移动时，计算可以与它们一起移动; 并行性是基于规模和活动而动态和透明的。这些指令分为三个概念类：存储器引用，包括负载，存储和特殊存储器结构指令; 控制流程包括叉，连接和分支; 并执行包括算术和比较指令。

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