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1. 发明申请

US20180060145A1 MESSAGE CACHE MANAGEMENT FOR MESSAGE QUEUES 有权
公开(公告)号：US20180060145A1
公开(公告)日：2018-03-01
申请号：US15254278
申请日：2016-09-01
申请人： Oracle International Corporation
发明人： Mukesh Jaiswal , Shubha Bose , James W. Stamos , Alan R. Downing , Devendra Singh
IPC分类号： G06F9/54 , G06F12/0875
CPC分类号： G06F9/546 , G06F12/0875 , G06F2209/548 , G06F2212/453
摘要： A method and apparatus for message cache management for message queues is provided. A plurality of messages from a plurality of enqueuers are enqueued in a queue comprising one or more shards, each shard comprising one or more subshards. A message cache is maintained in memory. Enqueuing a message includes enqueuing the message in a current subshard of a particular shard, which includes storing the message in a cached subshard corresponding to the current subshard of the particular shard. For each dequeuer-shard pair, a dequeue rate is determined. Estimated access time data is generated that includes an earliest estimated access time for each of a plurality of subshards based on the dequeuer-shard pair dequeue rates. A set of subshards is determined for storing as cached subshards in the message cache based on the earliest estimated access times for the plurality of subshards.

2. 发明申请

US20160314080A1 APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA 有权
公开(公告)号：US20160314080A1
公开(公告)日：2016-10-27
申请号：US15202279
申请日：2016-07-05
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F12/128
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

3. 发明申请

US20160313774A1 MULTI-CORE FUSE DECOMPRESSION MECHANISM 有权
公开(公告)号：US20160313774A1
公开(公告)日：2016-10-27
申请号：US15202330
申请日：2016-07-05
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F1/24 , G06F12/0875 , G06F9/44
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

4. 发明申请

US20150178218A1 MULTI-CORE MICROPROCESSOR CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM 有权
标题翻译：多核微处理器配置数据压缩和分解系统
公开(公告)号：US20150178218A1
公开(公告)日：2015-06-25
申请号：US14635969
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.
摘要翻译：一种装置具有熔丝阵列，器件编程器和多个核。熔丝阵列设置在管芯上，其中熔丝阵列包括多个半导体保险丝。器件编程器耦合到熔丝阵列，并被配置为访问配置数据，压缩配置数据以产生压缩的配置数据，并且使用压缩的配置数据对熔丝阵列进行编程。多个芯分别设置在管芯上，并且耦合到熔丝阵列，其中多个核中的每个核在加电/复位时访问和解压缩所有压缩的配置数据，以用于初始化每个多个核心。

5. 发明申请

US20150178216A1 CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE 有权
标题翻译：用于多核心的核心特定的保险丝机制
公开(公告)号：US20150178216A1
公开(公告)日：2015-06-25
申请号：US14635090
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.
摘要翻译：一种包括多个芯和一个熔丝阵列的装置。多个芯设置在模具上。熔丝阵列设置在管芯上并且耦合到多个芯中的每一个，其中熔丝阵列包括第一多个半导体熔丝和第二多个半导体熔丝。第一组多个半导体熔丝用多个芯中的每一个的压缩配置数据进行编程。所述第二多个半导体熔丝被编程为具有将所述压缩配置数据中的一些与所述多个核心中的一个相关联的核心指定数据，其中所述多个核心中的一个核心在上电时访问和解压缩所述一些压缩配置数据 /复位，用于初始化多个核心之一内的元件。

6. 发明申请

US20150178215A1 APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 有权
公开(公告)号：US20150178215A1
公开(公告)日：2015-06-25
申请号：US14635069
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F12/08 , G06F9/44
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

7. 发明授权

US09996404B2 Message cache management for message queues 有权
公开(公告)号：US09996404B2
公开(公告)日：2018-06-12
申请号：US15254278
申请日：2016-09-01
申请人： Oracle International Corporation
发明人： Mukesh Jaiswal , Shubha Bose , James W. Stamos , Alan R. Downing , Devendra Singh
IPC分类号： G06F3/00 , G06F9/44 , G06F9/48 , G06F13/00 , G06F9/54 , G06F12/0875
CPC分类号： G06F9/546 , G06F12/0875 , G06F2209/548 , G06F2212/453
摘要： A method and apparatus for message cache management for message queues is provided. A plurality of messages from a plurality of enqueuers are enqueued in a queue comprising one or more shards, each shard comprising one or more subshards. A message cache is maintained in memory. Enqueuing a message includes enqueuing the message in a current subshard of a particular shard, which includes storing the message in a cached subshard corresponding to the current subshard of the particular shard. For each dequeuer-shard pair, a dequeue rate is determined. Estimated access time data is generated that includes an earliest estimated access time for each of a plurality of subshards based on the dequeuer-shard pair dequeue rates. A set of subshards is determined for storing as cached subshards in the message cache based on the earliest estimated access times for the plurality of subshards.

8. 发明授权

US09727478B2 Apparatus and method for configurable redundant fuse banks 有权
公开(公告)号：US09727478B2
公开(公告)日：2017-08-08
申请号：US15209085
申请日：2016-07-13
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F13/12 , G06F12/0875 , G11C17/16 , G06F3/06 , G06F9/44 , G06F9/445 , G06F12/06 , G06F12/0806 , G11C17/18 , G11C29/00 , G06F11/10 , G06F12/0802 , G11C29/52 , G06F12/128 , G06F1/24 , G06F12/084 , G06F12/0811
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

9. 发明授权

US09483244B2 Compiling method and compiling device 有权
标题翻译：编译方法和编译器
公开(公告)号：US09483244B2
公开(公告)日：2016-11-01
申请号：US14638351
申请日：2015-03-04
申请人： FUJITSU LIMITED
发明人： Shigeru Kimura
IPC分类号： G06F9/45 , G06F12/08
CPC分类号： G06F8/4442 , G06F8/41 , G06F12/0862 , G06F12/0875 , G06F2212/453
摘要： A computer converts a source program into intermediate code. The computer detects, based on profile information related to a memory access for accessing target data stored in a memory, a memory access that fits an access pattern corresponding to an operating condition of a hardware prefetch function for the target data. The target data is data for which a prefetch instruction is to be inserted in advance. The prefetch instruction is an instruction for transferring data stored in the memory to a cache memory. The computer computes an evaluation value for the target data based on a length of successive memory accesses that fit the access pattern, and determines, based on the evaluation value, whether to suppress insertion of a prefetch instruction for the target data. The computer updates the intermediate code based on a result of the determination, and converts the updated intermediate code into a machine language program.
摘要翻译：计算机将源程序转换为中间代码。计算机基于与用于访问存储在存储器中的目标数据相关的存储器访问的简档信息，检测适合与目标数据的硬件预取功能的操作条件对应的访问模式的存储器访问。目标数据是预先插入预取指令的数据。预取指令是将存储在存储器中的数据传送到高速缓冲存储器的指令。计算机根据适合访问模式的连续存储器访问的长度来计算目标数据的评估值，并且基于评估值确定是否抑制对目标数据的预取指令的插入。计算机基于确定的结果更新中间代码，并将更新的中间代码转换为机器语言程序。

10. 发明申请

US20150178103A1 APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA 有权
公开(公告)号：US20150178103A1
公开(公告)日：2015-06-25
申请号：US14635006
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

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