专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US09311969B2 Systems and methods of storing data 有权
标题翻译：存储数据的系统和方法
公开(公告)号：US09311969B2
公开(公告)日：2016-04-12
申请号：US13329732
申请日：2011-12-19
申请人： Eran Sharon , Idan Alrod , Menahem Lasser
发明人： Eran Sharon , Idan Alrod , Menahem Lasser
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C7/10 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping.
摘要翻译：在具有控制器和存储器的数据存储装置中执行写入数据的方法。存储器包括锁存器和多个存储元件，并且可操作以根据比特序列到存储元件的状态的第一映射来在每个存储元件中存储第一数量的比特。该方法包括将数据位加载到存储器内的锁存器中，并通过使用一个或多个逻辑运算来操纵锁存器中的指定数据位来产生锁存器中的操纵数据位。该方法还包括根据第一映射将所操纵的数据位的组存储到该组存储元件的各个存储元件。指定的数据位根据比特序列到状态的第二映射对应于各个存储元件的状态。第二个映射与第一个映射不同。

72. 发明申请

US20160099078A1 DATA STORAGE DEVICE HAVING REFLOW AWARENESS 有权
标题翻译：具有反射意识的数据存储设备
公开(公告)号：US20160099078A1
公开(公告)日：2016-04-07
申请号：US14505034
申请日：2014-10-02
申请人： SANDISK TECHNOLOGIES INC.
发明人： TING LUO , JIANMIN HUANG , CHANGYUAN CHEN , GUIRONG LIANG
IPC分类号： G11C29/46 , G11C29/02 , G11C5/02
CPC分类号： G11C16/349 , G06F2201/81 , G11C7/20 , G11C29/025 , G11C29/46 , G11C2029/0407
摘要： A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value.
摘要翻译：一种方法包括：响应于在包括存储器的数据存储设备处的上电事件，读取存储在数据存储设备中的标志，并且确定该标志具有第一值，该第一值指示在以前没有检测到回流操作记忆。该方法还包括响应于确定标志具有第一值，在存储器处执行回流检测。该方法还包括响应于指示回流操作已经发生的回流检测，将该标志设置为第二值。

73. 发明申请

US20160099034A1 I/O PIN CAPACITANCE REDUCTION USING TSVS 有权
公开(公告)号：US20160099034A1
公开(公告)日：2016-04-07
申请号：US14969381
申请日：2015-12-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： Venkatesh Ramachandra , Farookh Moogat
IPC分类号： G11C8/12 , H01L25/18 , H01L23/48 , H01L25/065 , G11C16/06 , G11C29/02
CPC分类号： G11C8/12 , G11C16/06 , G11C29/023 , G11C29/025 , G11C29/028 , H01L23/481 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

74. 发明授权

US09305935B2 Multi-level contact to a 3D memory array and method of making 有权
公开(公告)号：US09305935B2
公开(公告)日：2016-04-05
申请号：US14631047
申请日：2015-02-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yao-Sheng Lee , Zhen Chen , Syo Fukata
IPC分类号： H01L27/115 , H01L29/66 , H01L27/108 , H01L21/768 , H01L29/792 , H01L23/48 , H01L27/11
CPC分类号： H01L27/11578 , H01L21/76816 , H01L21/76829 , H01L23/481 , H01L27/10802 , H01L27/11 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

75. 发明授权

US09305849B1 Method of making a three dimensional NAND device 有权
标题翻译：制造三维NAND器件的方法
公开(公告)号：US09305849B1
公开(公告)日：2016-04-05
申请号：US14539372
申请日：2014-11-12
申请人： SanDisk Technologies, Inc.
发明人： Masanori Tsutsumi , Shigehiro Fujino , Sateesh Koka , Senaka Kanakamedala , Yanli Zhang , Raghuveer S. Makala , Rahul Sharangpani , George Matamis , Wei Zhao
IPC分类号： H01L21/76 , H01L21/28 , H01L21/8239 , H01L21/283 , H01L27/115 , H01L21/822
CPC分类号： H01L21/8239 , H01L21/28282 , H01L21/8221 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的基本垂直于基板的主表面延伸的端部，基本上平行于基板的主表面延伸的多个控制栅电极，电荷存储材料位于多个控制栅电极和半导体沟道之间的层，位于电荷存储材料层和半导体沟道之间的隧道电介质，以及包含多个蛤状部分的阻挡电介质，每个具有两个水平部分的垂直部分一部分。多个控制栅电极中的每一个至少部分地位于蛤状阻挡电介质中的开口中，以及多个分立的覆盖氧化物段，其嵌入部分电荷存储材料层的厚度并位于阻挡电介质和电荷存储材料层。

76. 发明授权

US09293173B2 Non-volatile memory and method with peak current control 有权
标题翻译：具有峰值电流控制的非易失性存储器和方法
公开(公告)号：US09293173B2
公开(公告)日：2016-03-22
申请号：US14507647
申请日：2014-10-06
申请人： SanDisk Technologies Inc.
发明人： Dana Lee , Yi-Chieh Chen , Farookh Moogat
IPC分类号： G11C7/00 , G11C5/14 , G11C16/30
CPC分类号： G11C5/14 , G11C16/30
摘要： A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
摘要翻译：具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。负载信号总线以与系统功率容量成比例的强度被拉高。每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

77. 发明授权

US09281314B1 Non-volatile storage having oxide/nitride sidewall 有权
标题翻译：具有氧化物/氮化物侧壁的非挥发性存储体
公开(公告)号：US09281314B1
公开(公告)日：2016-03-08
申请号：US14511834
申请日：2014-10-10
申请人： SanDisk Technologies Inc.
发明人： Takashi Kashimura , Xiaolong Hu , Sayako Nagamine , Yusuke Yoshida , Hiroaki Iuchi , Akira Nakada , Kazutaka Yoshizawa
IPC分类号： H01L29/792 , H01L21/336 , H01L27/115 , H01L21/768 , H01L23/528 , H01L23/532 , H01L21/285 , H01L21/28 , H01L21/02 , H01L21/764 , H01L21/311
CPC分类号： H01L27/1157 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L27/11524 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Non-volatile storage devices and methods for fabricating non-volatile storage device are described. Sidewalls of the memory cells and their associated word line may be covered with silicon oxide. Silicon nitride covers the silicon oxide adjacent to the word lines, which may provide protection for the word lines during fabrication. However, silicon nitride can trap charges, which can degrade operation if the trapped charges are near a charge trapping region of a memory cell. Thus, the silicon nitride does not cover the silicon oxide adjacent to charge storage regions of the memory cells, which can improve device operation. For example, memory cell current may be increased. Techniques for forming such a device are also disclosed. One aspect includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device.
摘要翻译：描述了用于制造非易失性存储装置的非易失性存储装置和方法。存储器单元的侧壁及其相关联的字线可以用氧化硅覆盖。氮化硅覆盖与字线相邻的氧化硅，这可以在制造期间为字线提供保护。然而，氮化硅可以捕获电荷，如果捕获的电荷接近存储器单元的电荷捕获区域，则可能降低操作。因此，氮化硅不覆盖与存储单元的电荷存储区域相邻的氧化硅，这可以改善器件工作。例如，可以增加存储单元电流。还公开了用于形成这种装置的技术。一个方面包括在形成存储器件时使用牺牲材料来控制氮化硅层的形成的方法。

78. 发明申请

US20160064090A1 Charge Redistribution During Erase In Charge Trapping Memory 有权
公开(公告)号：US20160064090A1
公开(公告)日：2016-03-03
申请号：US14851639
申请日：2015-09-11
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/14 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.

79. 发明申请

US20160062657A1 DYNAMIC HOST COMMAND REJECTION 有权
标题翻译：动态主机命令拒绝
公开(公告)号：US20160062657A1
公开(公告)日：2016-03-03
申请号：US14484106
申请日：2014-09-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： OFER SHINAAR , NATI RAPAPORT , EFRAIM DALUMI , ERAN ARAD , YIFTACH TZORI
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F3/0607 , G06F3/0659
摘要： A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.
摘要翻译：数据存储设备包括非易失性存储器和主机接口电路。主机接口电路被配置为响应于从主机设备接收到第一命令来访问表以基于数据存储设备的操作状态来确定是否拒绝第一命令。数据存储设备还包括耦合到非易失性存储器和主机接口电路的处理器。处理器配置为对表进行编程。

80. 发明申请

US20160054937A1 TEMPERATURE ACCELERATED STRESS TIME 有权
标题翻译：温度加速应力时间
公开(公告)号：US20160054937A1
公开(公告)日：2016-02-25
申请号：US14510771
申请日：2014-10-09
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Dana Lee , Henry Chin , Abhijeet Manohar
IPC分类号： G06F3/06
CPC分类号： G11C16/3495 , G11C7/04
摘要： A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions.
摘要翻译：存储器系统或闪存卡可能暴露于经过时间或升高的温度条件，这可能降低存储器。例如，延长的时间段或高温条件可能阻碍存储器设备中的数据保留。经过的时间和温度条件的估计可能对于存储器管理是有用的。周期性地识别存储器设备中的一个或多个前哨块并且测量那些哨兵块中的数据保持位移的算法可以计算近似经过的时间和/或温度条件的组合效应的标量值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式