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71. 发明授权

US07808018B2 Solid-state imaging apparatus 失效
标题翻译：固态成像装置
公开(公告)号：US07808018B2
公开(公告)日：2010-10-05
申请号：US11941096
申请日：2007-11-16
申请人： Akira Uemura
发明人： Akira Uemura
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H04N5/37213 , H01L27/148 , H04N5/3692
摘要： A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.
摘要翻译：一种固态成像装置，包括：像素阵列，包括以电荷转移方向设置的多个光接收元件，所述多个光接收元件将光信号转换成电信号;第一电荷转移单元和第二电荷转移单元布置在像素阵列的每侧，并且在电荷传输方向上传送从像素阵列输入的信号电荷，连接到第一电荷转移单元的第一浮动扩散区域，连接到第二电荷转移单元的第二浮动扩散区域，连接第一浮动扩散区域和第二浮动扩散区域的布线层，以及连接到布线层的输出电路，并根据第一浮动扩散区域和第二浮动扩散区域的电位输出信号电压。

72. 发明授权

US07807531B2 Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps 失效
标题翻译：具有沟槽式栅极的半导体器件及其制造方法能够简化制造步骤
公开(公告)号：US07807531B2
公开(公告)日：2010-10-05
申请号：US12453551
申请日：2009-05-14
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4925 , H01L29/511 , H01L29/518 , H01L29/66734
摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.
摘要翻译：在半导体器件中，在半导体晶片的沟槽内形成栅极二氧化硅层。第一栅电极经由栅极二氧化硅层形成在半导体晶片的沟槽的侧壁上。绝缘层经由栅极二氧化硅层形成在半导体晶片的沟槽的底部上并被第一栅电极包围。绝缘层不包括二氧化硅，并且具有与二氧化硅不同的蚀刻特性。第二栅电极被埋在半导体晶片的沟槽中，并与第一栅电极和绝缘层接触。

73. 发明申请

US20100244285A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100244285A1
公开(公告)日：2010-09-30
申请号：US12659762
申请日：2010-03-19
申请人： Hirofumi Fukuda
发明人： Hirofumi Fukuda
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/3135 , H01L21/561 , H01L24/02 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082
摘要： In a semiconductor device, corner portions of a inner insulating film are chamfered, and hence a damage is less likely to reach the corner portion of the inner insulating film, though the corner portion of an outer insulating film is damaged. Therefore, a hermeticity of a semiconductor element can be effectively maintained, and the yield of semiconductor pellets can be improved. Moreover, since it is not necessary to chamfer the corner portion of the outer insulating film, the structure remains simple and the productivity can be improved.
摘要翻译：在半导体装置中，内绝缘膜的角部被倒角，由于外绝缘膜的角部被破坏，因此损伤不太可能到达内绝缘膜的角部。因此，能够有效地保持半导体元件的气密性，能够提高半导体芯片的成品率。此外，由于不需要对外绝缘膜的角部进行倒角，所以结构保持简单，并且可以提高生产率。

74. 发明申请

US20100242002A1 Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method 失效
标题翻译：用于分析复合材料层的结构的方法和装置，以及用于使计算机执行该方法的存储介质存储程序
公开(公告)号：US20100242002A1
公开(公告)日：2010-09-23
申请号：US12659399
申请日：2010-03-08
申请人： Tomohisa Sekiguchi
发明人： Tomohisa Sekiguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , H05K1/0271 , H05K3/0005
摘要： A structure analysis apparatus (1) for analyzing structure of a complex material layer containing a plurality of members (2a, 2b) for modeling layout data on a complex material layer, includes: an area setting portion (21) for setting an area to be modeled in the complex material layer; an area dividing portion (22) for dividing the area into a plurality of elements; an area computing portion (23) for calculating, based on an occupancy of each of the plurality of members (2a, 2b) in the area, the number of elements corresponding respectively to the plurality of members (2a, 2b); and an element placing portion (24) for generating a model of the complex material layer by placing the plurality of members (2a, 2b) respectively in the plurality of elements based on the number of the elements corresponding respectively to the plurality of members (2a, 2b).
摘要翻译：一种用于分析复合材料层的结构的结构分析装置（1），其包含用于对复合材料层上的布局数据进行建模的多个构件（2a，2b）的构造，包括：区域设定部（21），其将区域设定为模拟在复杂的材料层; 区域划分部分（22），用于将该区域分成多个元素; 基于所述多个构件（2a，2b）中的每一个在所述区域中的占有率来计算分别对应于所述多个构件（2a，2b）的元件的数量的区域计算部分（23）。以及用于通过基于分别对应于多个构件（2a）的元件的数量将多个构件（2a，2b）分别放置在多个元件中来生成复合材料层的模型的元件放置部分（24），2b）。

75. 发明申请

US20100241927A1 Apparatus and method for data processing 有权
标题翻译：数据处理装置及方法
公开(公告)号：US20100241927A1
公开(公告)日：2010-09-23
申请号：US12659685
申请日：2010-03-17
申请人： Yoshitaka Soma
发明人： Yoshitaka Soma
IPC分类号： H03M13/05 , H03M13/09 , H03M13/43 , G06F11/07 , G06F11/10
CPC分类号： G06F11/1052 , G11C29/848
摘要： A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.
摘要翻译：数据处理装置包括被配置为存储存储数据的非易失性半导体存储器和被配置为生成附加数据并将附加数据添加到主存储数据的附加数据控制电路，并且附加数据在第一模式和第二模式。附加数据控制电路包括被配置为在第一模式中生成附加数据的第一模式电路; 以及第二模式电路，被配置为在第二模式中生成附加数据。存储数据包含作为主存储数据和附加数据的目标数据或目标数据的反转数据。

76. 发明申请

US20100238744A1 Semiconductor stroage device 有权
标题翻译：半导体脉冲装置
公开(公告)号：US20100238744A1
公开(公告)日：2010-09-23
申请号：US12656597
申请日：2010-02-04
申请人： Nobumitsu Yano
发明人： Nobumitsu Yano
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4094
摘要： A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.
摘要翻译：半导体存储装置包括：电平移位单元，当读出放大器开始读取位线的电位时，移位位线对BL的电位，BLB。电平移位单元包括电平移位电容器和定时发生器。每个电平移动电容器具有连接到每个位线的一个电极，并且对于每个位线对由两个电平移位电容器形成一对电极。定时发生器共同连接到电平移动电容器的每个其他电极，并且将移位电容器驱动信号提供给其它电极的公共节点，以便将电平移动电容器的存储电量改变为预定的定时。

77. 发明授权

US07800601B2 Display control method and apparatus 有权
标题翻译：显示控制方法和装置
公开(公告)号：US07800601B2
公开(公告)日：2010-09-21
申请号：US11819293
申请日：2007-06-26
申请人： Makoto Miura
发明人： Makoto Miura
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3655 , G09G2310/027 , G09G2310/0297 , G09G2310/08 , G09G2330/021 , G09G2330/023 , G09G2340/0428
摘要： Disclosed is a display controlling apparatus including latch circuits for holding color data of a current line and a previous line, a latch circuit for holding a polarity signal of the previous line, and a recovery control circuit. The recovery control circuit controls a recovery switch from color data of the previous and current lines, a polarity signal and a recovery clock. For both driving method employing frame-based common inverting and the driving method employing line-based common inverting, the display/controlling apparatus recovers electric charge efficiently to provide for low power dissipation.
摘要翻译：公开了一种显示控制装置，包括用于保持当前行和前一行的彩色数据的锁存电路，用于保持前一行的极性信号的锁存电路和恢复控制电路。恢复控制电路根据前一行和当前行的颜色数据，极性信号和恢复时钟控制恢复开关。对于采用基于帧的公共反相的驱动方法和采用基于线的公共反相的驱动方法，显示/控制装置有效地恢复电荷以提供低功耗。

78. 发明授权

US07800108B2 Semiconductor device and method of manufacturing semiconductor device including optical test pattern above a light shielding film 有权
标题翻译：半导体器件及其制造方法，其包括在遮光膜上方的光学测试图案的半导体器件
公开(公告)号：US07800108B2
公开(公告)日：2010-09-21
申请号：US12323614
申请日：2008-11-26
申请人： Hidetaka Nambu
发明人： Hidetaka Nambu
IPC分类号： H01L23/58 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76229
摘要： The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.
摘要翻译：本发明的半导体器件包括在具有第一区域和第二区域的基板上的第一绝缘膜，形成在第一区域中的遮光膜和形成在第一绝缘膜中的第二区域中的互连膜，第二绝缘膜绝缘膜，其具有在所述第一区域中的所述遮光膜上方的第一凹部，以及在所述第一绝缘膜上的所述第二绝缘膜中的所述第二区域中具有通路孔和第二凹部的配线孔，屏蔽膜与第一多个凹部的区域重叠。

79. 发明申请

US20100231569A1 Display panel driver and display apparatus using the same 有权
标题翻译：显示面板驱动器及使用其的显示装置
公开(公告)号：US20100231569A1
公开(公告)日：2010-09-16
申请号：US12659452
申请日：2010-03-09
申请人： Atsushi Shimatani
发明人： Atsushi Shimatani
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3696 , G09G2310/0218 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G09G2310/0297 , G09G2330/02 , G09G2330/021
摘要： In a display panel driver an output amplifier circuit includes a first output stage to receive a power supply voltage and a first voltage lower thereto and to output a drive voltage in a first voltage range defined between the power supply voltage and a middle power supply voltage; and a second output stage to receive the power supply and ground voltages and to output a drive voltage between the power supply and ground voltages. In a first mode that the first voltage is set as the middle power supply voltage, the first output stage outputs a first drive voltage in the first voltage range to one of first and second output terminals. In a second mode that the first voltage is set as the ground voltage, the second output stage outputs a first drive voltage in the first voltage range to one of the first and second output terminals.
摘要翻译：在显示面板驱动器中，输出放大器电路包括：第一输出级，用于接收电源电压和低于其的第一电压，并输出在电源电压和中间电源电压之间限定的第一电压范围内的驱动电压; 以及第二输出级，用于接收电源和接地电压并输出电源和接地电压之间的驱动电压。在第一模式中，第一电压被设置为中间电源电压，第一输出级将第一电压范围中的第一驱动电压输出到第一和第二输出端之一。在将第一电压设置为接地电压的第二模式中，第二输出级将第一电压范围内的第一驱动电压输出到第一和第二输出端之一。

80. 发明申请

US20100231428A1 TRACK-AND-HOLD CIRCUIT AND A/D CONVERTER 有权
标题翻译：跟踪保持电路和A / D转换器
公开(公告)号：US20100231428A1
公开(公告)日：2010-09-16
申请号：US12717527
申请日：2010-03-04
申请人： Yuji NAKAJIMA
发明人： Yuji NAKAJIMA
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , G11C27/024 , H03M1/1023 , H03M1/141
摘要： A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit.
摘要翻译：轨道保持电路包括对模拟输入信号进行采样的第一采样电路，对模拟输入信号进行采样的第二采样电路，并联连接的第二采样电路和第一采样电路;第一放大器，从第一采样电路输出的信号，以及放大从第二采样电路输出的信号的第二放大器。

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