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71. 发明申请

US20080162852A1 Tier-based memory read/write micro-command scheduler 审中-公开
标题翻译：基于层次的内存读/写微命令调度程序
公开(公告)号：US20080162852A1
公开(公告)日：2008-07-03
申请号：US11647985
申请日：2006-12-28
申请人： Surya Kareenahalli , Zohar Bogin
发明人： Surya Kareenahalli , Zohar Bogin
IPC分类号： G06F13/00
CPC分类号： G06F12/0215
摘要： A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.
摘要翻译：描述了一种方法，装置和系统。在一个实施例中，该方法包括接收多个存储器请求的芯片组，其中每个存储器请求包括一个或多个微命令，每个微命令需要一个或多个存储器时钟周期来执行，并且调度每个微命令的执行从多个存储器请求中的多于一个的顺序，以减少完成执行多于一个存储器请求所需的总存储器时钟周期的数量。

72. 发明申请

US20080144405A1 Data strobe timing compensation 审中-公开
标题翻译：数据选通定时补偿
公开(公告)号：US20080144405A1
公开(公告)日：2008-06-19
申请号：US11642318
申请日：2006-12-18
申请人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G11C7/10
CPC分类号： G06F13/4239
摘要： A method, apparatus, and system are disclosed. In one embodiment, the method receiving data from a memory on a first interconnect of at least one interconnect, receiving a source-synchronous data strobe from the memory, creating at least a nominal, an early, and a delayed compensated data strobe from the received data strobe, latching the received data with the nominal, early, or delayed compensated data strobe, outputting the latched data onto one or more of the at least one interconnect.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法从至少一个互连的第一互连上的存储器接收数据，从存储器接收源同步数据选通脉冲，从接收到的数据选通产生至少一个标称，早期和延迟补偿的数据选通数据选通，使用标称，早期或延迟补偿的数据选通来锁存所接收的数据，将锁存的数据输出到所述至少一个互连中的一个或多个上。

73. 发明授权

US07370125B2 Stream under-run/over-run recovery 失效
标题翻译：流下运行/超跑恢复
公开(公告)号：US07370125B2
公开(公告)日：2008-05-06
申请号：US10723135
申请日：2003-11-25
申请人： Zohar Bogin , Brent D. Chartrand , Arthur D. Hunter, Jr. , Mihir Shah
发明人： Zohar Bogin , Brent D. Chartrand , Arthur D. Hunter, Jr. , Mihir Shah
IPC分类号： G06F13/12 , G06F15/16
CPC分类号： G06F3/16 , G10L19/0018
摘要： Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.
摘要翻译：描述了机器可读介质，方法和装置，以从流下运行和/或超载条件中恢复。在一些实施例中，音频控制器可以丢弃流的任何部分采样块。

74. 发明授权

US07346716B2 Tracking progress of data streamer 有权
标题翻译：跟踪数据流的进度
公开(公告)号：US07346716B2
公开(公告)日：2008-03-18
申请号：US10723347
申请日：2003-11-25
申请人： Zohar Bogin , Brent D. Chartrand , Arthur D. Hunter, Jr.
发明人： Zohar Bogin , Brent D. Chartrand , Arthur D. Hunter, Jr.
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.
摘要翻译：描述了机器可读介质，方法和装置，以在系统存储器中的编解码器和缓冲器之间流式传输数据，并维持指示缓冲器中当前位置的系统存储器中的值。在一些实施例中，音频控制器通过具有放松排序规则的同步信道将数据流传输到系统存储器中的缓冲器，并且通过跨同步信道的写入更新指示当前位置的值到系统存储器。

75. 发明授权

US07343469B1 Remapping I/O device addresses into high memory using GART 有权
标题翻译：使用GART将I / O设备地址重新映射到高内存中
公开(公告)号：US07343469B1
公开(公告)日：2008-03-11
申请号：US09667050
申请日：2000-09-21
申请人： Zohar Bogin , Jeffrey L. Rabe
发明人： Zohar Bogin , Jeffrey L. Rabe
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F12/1027
摘要： An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.
摘要翻译：一种地址转换装置和方法，其可以将有限范围的存储器地址从外围设备转换为扩展存储器地址。本发明可以将诸如具有4GB地址范围的PCI总线等外围总线的有限地址能力扩展到更大的地址能力，例如64GB的地址范围。这种转换可以由硬件在飞行中执行，因此不会产生明显的传输时间延迟。可以通过向传统图形控制器接口添加特征来实现转换，从而最小化对电路复杂性和系统成本的影响。

76. 发明申请

US20070233943A1 Dynamic update adaptive idle timer 失效
标题翻译：动态更新自适应空闲定时器
公开(公告)号：US20070233943A1
公开(公告)日：2007-10-04
申请号：US11394461
申请日：2006-03-30
申请人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F12/0215
摘要： Embodiments of dynamic update adaptive idle timer are presented herein.
摘要翻译：本文给出了动态更新自适应空闲定时器的实施例。

77. 发明授权

US07230627B2 Optimized memory addressing 有权
标题翻译：优化的内存寻址
公开(公告)号：US07230627B2
公开(公告)日：2007-06-12
申请号：US10796686
申请日：2004-03-08
申请人： David E. Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David E. Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399 , G09G5/39 , G06F13/00
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
摘要翻译：本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

78. 发明申请

US20070005934A1 High performance chipset prefetcher for interleaved channels 有权
标题翻译：用于交错通道的高性能芯片组预取器
公开(公告)号：US20070005934A1
公开(公告)日：2007-01-04
申请号：US11172401
申请日：2005-06-29
申请人： Hemant Rotithor , Abhishek Singhal , Randy Osborne , Zohar Bogin , Raul Gutierrez , Buderya Acharya , Surya Kareenahalli
发明人： Hemant Rotithor , Abhishek Singhal , Randy Osborne , Zohar Bogin , Raul Gutierrez , Buderya Acharya , Surya Kareenahalli
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0607 , G06F2212/6022 , G06F2212/6026
摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.
摘要翻译：本发明包括一种从具有交织信道的存储装置预取的装置和方法。芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。

79. 发明授权

US06961823B2 Stream-down prefetching cache 失效
标题翻译：流式预取缓存
公开(公告)号：US06961823B2
公开(公告)日：2005-11-01
申请号：US10628434
申请日：2003-07-29
申请人： Herbert Hing-Jing Hum , Zohar Bogin
发明人： Herbert Hing-Jing Hum , Zohar Bogin
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： An apparatus and method for prefetching cache data in response to data requests. The prefetching uses the memory addresses of requested data to search for other data, from a related address, in a cache. This, or other data, may then be prefetched based on the result of the search.
摘要翻译：一种用于响应于数据请求预取缓存数据的装置和方法。预取使用请求的数据的存储器地址从缓存中的相关地址搜索其他数据。然后可以基于搜索的结果来预取这个或其他数据。

80. 发明申请

US20050198542A1 Method and apparatus for a variable memory enable deassertion wait time 审中-公开
标题翻译：用于可变存储器的方法和装置使得不允许等待时间成为可能
公开(公告)号：US20050198542A1
公开(公告)日：2005-09-08
申请号：US10796366
申请日：2004-03-08
申请人： David Freker , Anoop Mukker , Zohar Bogin
发明人： David Freker , Anoop Mukker , Zohar Bogin
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F13/1668 , Y02D10/171
摘要： An integrated circuit designed to be coupled to a suspendable memory, the integrated circuit comprising a memory enable deassertion delay (MEDD) logic setting a wait period for the deassertion of a memory enable signal after completion of a memory operation. The wait period is chosen for a preferred latency versus power savings tradeoff.
摘要翻译：一种被设计为耦合到可挂起存储器的集成电路，所述集成电路包括存储器使能解除延迟（MEDD）逻辑，其设置在完成存储器操作之后解除存储器使能信号的等待周期。选择等待时间为优先等待时间与功率节省权衡。

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