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71. 发明授权

US06197631B1 Semiconductor storage device with a capacitor using a ferroelectric substance and fabricating method thereof 失效
标题翻译：具有使用铁电体的电容器的半导体存储装置及其制造方法
公开(公告)号：US06197631B1
公开(公告)日：2001-03-06
申请号：US09168235
申请日：1998-10-07
申请人： Kazuya Ishihara
发明人： Kazuya Ishihara
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01L27/10852
摘要： In a fabricating method of a semiconductor storage device, a ferroelectric film is formed on a lower electrode, and crystallized. Thereafter, a heat treatment is performed in an atmosphere of hydrogen or a mixture of hydrogen and an inert gas to vanish a defect at the interface between the gate insulating film of a MOS transistor and a silicon substrate. Next, an upper electrode is formed on the ferroelectric film.
摘要翻译：在半导体存储装置的制造方法中，在下部电极上形成铁电体膜，并使其结晶化。此后，在氢气或惰性气体的混合气氛中进行热处理，以清除MOS晶体管的栅极绝缘膜与硅衬底之间的界面处的缺陷。接着，在铁电体膜上形成上部电极。

72. 发明授权

US6125432A Image process apparatus having a storage device with a plurality of banks storing pixel data, and capable of precharging one bank while writing to another bank 失效
标题翻译：具有存储装置的图像处理装置具有存储像素数据的多个存储体，并且能够在写入另一个存储体时对一个存储体进行预充电
公开(公告)号：US6125432A
公开(公告)日：2000-09-26
申请号：US903348
申请日：1997-07-30
申请人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
发明人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
IPC分类号： G06F12/06 , G06F12/00 , G06T1/60 , G09G5/39 , G09G5/399 , G11C11/401 , G11C11/407 , H04N7/50 , G06F12/02
CPC分类号： G09G5/39 , H04N19/423 , H04N19/61 , G09G2340/02 , G09G2360/123 , G09G5/399
摘要： Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.
摘要翻译：屏幕数据由两组现场数据组成。每组场数据被分成多个数据块，其具有与垂直排列的四行像素对应的四行像素数据。对应于一组场数据的每个数据块被存储在帧缓冲存储器的第一存储体（存储体0）中，而与另一组场数据相对应的数据块存储在第二存储体（存储体1）中）。一行地址分配给每个数据块。 Bank1被预充电，而bank0处于写操作，反之亦然，以便同时执行预充电操作和写操作，使得可以以高数据传输速率传输像素数据，并且两组现场数据可以独立转让

73. 发明授权

US5651123A Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
标题翻译：具有符合M系列伪随机数序列的寻址能力的程序执行控制装置
公开(公告)号：US5651123A
公开(公告)日：1997-07-22
申请号：US460947
申请日：1995-06-05
申请人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami , Hiroshi Segawa , Tetsuya Matsumura
发明人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami , Hiroshi Segawa , Tetsuya Matsumura
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/321 , G06F2207/7219
摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.
摘要翻译：程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器，以及来自指令解码器的跳转地址和选择信号。结果，从指令存储器中读取指令并按程序地址的顺序执行。反馈移位寄存器可以实现为小规模电路并且可以高速运行。

74. 发明授权

US5397446A Method of forming a ferroelectric film 失效
标题翻译：形成铁电体膜的方法
公开(公告)号：US5397446A
公开(公告)日：1995-03-14
申请号：US84152
申请日：1993-07-01
申请人： Kazuya Ishihara , Shigeo Onishi
发明人： Kazuya Ishihara , Shigeo Onishi
IPC分类号： C23C14/34 , C23C14/00 , C23C14/08 , C23C14/54 , H01B3/00 , H01L21/31 , H01L21/316 , H01L21/3205 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/105
CPC分类号： C23C14/0036 , C23C14/08 , H01L21/3205
摘要： A method of forming a ferroelectric film on a heated support is provided which includes the steps of forming a first layer on the heated support by sputtering a material including lead at a first pressure; and forming a second layer on the first layer by sputtering the material at a second pressure, the second pressure being lower than the first pressure.
摘要翻译：提供了一种在加热的支撑体上形成铁电体膜的方法，其包括以下步骤：通过在第一压力下溅射包括铅的材料在加热的支撑体上形成第一层; 以及通过在第二压力下溅射所述材料在所述第一层上形成第二层，所述第二压力低于所述第一压力。

75. 发明授权

US5394355A Read only memory for storing multi-data 失效
标题翻译：只读存储器用于存储多数据
公开(公告)号：US5394355A
公开(公告)日：1995-02-28
申请号：US109509
申请日：1993-08-20
申请人： Shinichi Uramoto , Tetsuya Matsumura , Masahiko Yoshimoto , Kazuya Ishihara , Hiroshi Segawa
发明人： Shinichi Uramoto , Tetsuya Matsumura , Masahiko Yoshimoto , Kazuya Ishihara , Hiroshi Segawa
IPC分类号： G11C11/56 , G11C17/00
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译：只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。通过切换参考电位传输线的电位来改变存储单元中的存储数据。这使得能够将不同的数据位存储在一个存储单元中。

76. 发明授权

US5375079A Arithmetical unit including accumulating operation 失效
标题翻译：算术单位包括累积运行
公开(公告)号：US5375079A
公开(公告)日：1994-12-20
申请号：US009529
申请日：1993-01-27
申请人： Shinichi Uramoto , Kazuya Ishihara
发明人： Shinichi Uramoto , Kazuya Ishihara
IPC分类号： G06F7/50 , G06F7/507 , G06F7/509 , G06F7/544 , G06F7/38
CPC分类号： G06F7/5095 , G06F7/544 , G06F2207/5442
摘要： An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N
摘要翻译：用于增加速度和减小电路尺寸的改进的M位累加器包括N位（N

77. 发明授权

US08451647B2 Resistance control method for nonvolatile variable resistive element 失效
标题翻译：非易失性可变电阻元件的电阻控制方法
公开(公告)号：US08451647B2
公开(公告)日：2013-05-28
申请号：US13157620
申请日：2011-06-10
申请人： Kazuya Ishihara
发明人： Kazuya Ishihara
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0083 , G11C2013/0088 , G11C2213/79
摘要： A resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device is provided. The device includes a memory cell array in which unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a memory operation are selected by first selection lines (word lines), second selection lines (bit lines) and third selection lines (source lines). The method includes steps of selecting one or more first selection lines, selecting a plurality of second selection lines, and applying a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation, such that the voltage necessary for the memory operation is applied to all of the selected memory cells.
摘要翻译：提供了一种用于非易失性半导体存储器件中的非易失性可变电阻元件的电阻控制方法。该器件包括存储单元阵列，其中具有非易失性可变电阻元件和晶体管的单元存储单元排列成矩阵。通过第一选择线（字线），第二选择线（位线）和第三选择线（源极线）来选择作为存储器操作的目标的存储器单元。该方法包括以下步骤：选择一个或多个第一选择线，选择多个第二选择线，以及施加补偿电压，其中由通过第二选择流入第三选择线的电流引起的第三选择线的电位变化线路以对于存储器操作所必需的电压进行补偿，使得存储器操作所需的电压被应用于所选择的所有存储单元。

78. 发明授权

US08400830B2 Nonvolatile semiconductor memory device and driving method therefor 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08400830B2
公开(公告)日：2013-03-19
申请号：US13131388
申请日：2009-11-18
申请人： Yutaka Ishikawa , Kazuya Ishihara , Yoshiji Ohta
发明人： Yutaka Ishikawa , Kazuya Ishihara , Yoshiji Ohta
IPC分类号： G11C11/34
CPC分类号： G11C7/1006 , G11C8/10 , G11C13/0007 , G11C13/0069 , G11C2013/0076 , G11C2213/79
摘要： A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.
摘要翻译：一种非易失性半导体存储器件，其中可以延长存储器单元寿命，同时使得可以以位为单位执行写入。当命令信息表示写入时，比较单元37将目标存储器单元中的写入数据与写入目标数据进行比较，以便在写入/读取控制单元40给出比较结果时，当比较结果表示匹配时，写入/读取控制单元40 不指示解码器单元（51A，51B和53）在目标存储单元中执行写入，并且当比较结果表示不匹配时，写入/读取控制单元40指示解码器单元将写入目标数据写入到目标存储单元

79. 发明申请

US20120075911A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120075911A1
公开(公告)日：2012-03-29
申请号：US13224814
申请日：2011-09-02
申请人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097
摘要： Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.
摘要翻译：无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。此外，存储单元阵列由偶数个子库构成，并且将擦除电压脉冲应用于一个子库中，并且编程电压脉冲在另一个子库中的应用被交替执行。

80. 发明申请

US20110238902A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD 有权
标题翻译：非易失性半导体存储器件和驱动方法
公开(公告)号：US20110238902A1
公开(公告)日：2011-09-29
申请号：US13131388
申请日：2009-11-18
申请人： Yutaka Ishikawa , Kazuya Ishihara , Yoshiji Ohta
发明人： Yutaka Ishikawa , Kazuya Ishihara , Yoshiji Ohta
IPC分类号： G06F12/02
CPC分类号： G11C7/1006 , G11C8/10 , G11C13/0007 , G11C13/0069 , G11C2013/0076 , G11C2213/79
摘要： A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.
摘要翻译：一种非易失性半导体存储器件，其中可以延长存储器单元寿命，同时使得可以以位为单位执行写入。当命令信息表示写入时，比较单元37将目标存储器单元中的写入数据与写入目标数据进行比较，以便在写入/读取控制单元40给出比较结果时，当比较结果表示匹配时，写入/读取控制单元40 不指示解码器单元（51A，51B和53）在目标存储单元中执行写入，并且当比较结果表示不匹配时，写入/读取控制单元40指示解码器单元将写入目标数据写入到目标存储单元

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