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71. 发明申请

US20120128516A1 COMPRESSOR 有权
标题翻译：压缩机
公开(公告)号：US20120128516A1
公开(公告)日：2012-05-24
申请号：US13387465
申请日：2009-12-02
申请人： Kang-Wook Lee , Jin-Ung Shin , Geun-Hyung Lee , Seoung-Min Kang
发明人： Kang-Wook Lee , Jin-Ung Shin , Geun-Hyung Lee , Seoung-Min Kang
IPC分类号： F04B17/00
CPC分类号： F04C18/3564 , F01C21/02 , F04C18/322 , F04C23/008 , F04C23/02 , F04C29/0071 , F04C29/0085 , F04C29/023 , F04C2230/603 , F04C2240/10 , F04C2240/30 , F04C2240/40 , F04C2240/52 , F04C2240/60 , F04C2270/12
摘要： The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. As the rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, components can be easily centered and assembled with the structural stability. In addition, the oil stored in a hermetic container is supplied to a lubrication passage provided between the rotary member and the stationary member. This reduces a friction loss between the components and achieves the operation reliability. Moreover, the oil is easily introduced into a vane mounting hole in which a vane is linearly reciprocated. This reduces the friction and abrasion of the vane and improves the operation reliability.
摘要翻译：本发明涉及一种压缩机，其中悬挂在静止构件上的旋转构件旋转以压缩制冷剂。由于旋转构件悬挂在第一静止构件上并且可旋转地支撑在与第一固定构件间隔开的第二固定构件上，因此可以容易地使组件以结构稳定性居中和组装。此外，存储在密封容器中的油被供给到设置在旋转构件和固定构件之间的润滑通道。这减少了部件之间的摩擦损失并实现了操作的可靠性。此外，油容易地引入到叶片线性往复运动的叶片安装孔中。这降低了叶片的摩擦和磨损，提高了操作的可靠性。

72. 发明申请

US20120128511A1 COMPRESSOR 有权
标题翻译：压缩机
公开(公告)号：US20120128511A1
公开(公告)日：2012-05-24
申请号：US13388116
申请日：2009-12-02
申请人： Kang-Wook Lee , Jang-Woo Lee , Bum-Dong Sa , Jin-Ung Shin
发明人： Kang-Wook Lee , Jang-Woo Lee , Bum-Dong Sa , Jin-Ung Shin
IPC分类号： F04B35/04
CPC分类号： F01C21/02 , F04C18/322 , F04C18/3564 , F04C23/008 , F04C23/02 , F04C29/0071 , F04C29/0085 , F04C29/023 , F04C2230/603 , F04C2240/10 , F04C2240/30 , F04C2240/40 , F04C2240/52 , F04C2240/60 , F04C2270/12
摘要： The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. The rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member to thereby achieve the structural stability, improve the operation reliability and reduce the vibration. The components can be easily centered and assembled with an excellent assembly property. In addition, a mounting structure of an elastically-supported vane is improved to ensure the lubrication performance and the operation reliability. Moreover, a mounting structure of a roller-incorporated vane is improved to reduce vibration and prevent refrigerant leakage, which leads to high compression efficiency.
摘要翻译：本发明涉及一种压缩机，其中悬挂在静止构件上的旋转构件旋转以压缩制冷剂。旋转构件悬挂在第一固定构件上并且可旋转地支撑在与第一固定构件间隔开的第二固定构件上，从而实现结构稳定性，提高操作可靠性并减少振动。组件可以容易地集中和组装，具有优异的组装性能。此外，改进了弹性支撑叶片的安装结构，以确保润滑性能和操作可靠性。此外，改进了带辊子的叶片的安装结构以减少振动并防止制冷剂泄漏，这导致高的压缩效率。

73. 发明授权

US08004848B2 Stack module, card including the stack module, and system including the stack module 有权
标题翻译：堆叠模块，包括堆叠模块的卡，以及包括堆栈模块的系统
公开(公告)号：US08004848B2
公开(公告)日：2011-08-23
申请号：US12126313
申请日：2008-05-23
申请人： Seung-Duk Baek , Mitsuo Umemoto , Kang-Wook Lee
发明人： Seung-Duk Baek , Mitsuo Umemoto , Kang-Wook Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541
摘要： Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.
摘要翻译：提供了通过使用简化的处理以低成本制造的高可靠性堆栈模块，使用堆栈模块的卡和使用堆栈模块的系统。在堆叠模块中，单元基板相对于彼此层叠，并且每个单元基板包括选择端子。第一选择线电连接到设置在奇数层的第一单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。第二选择线电连接到以偶数层布置的第二单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。选择端子设置在第一选择线和第二选择线之间。

74. 发明申请

US20110086486A1 Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein 有权
标题翻译：形成具有垂直扩展的基板通孔的集成电路芯片的方法
公开(公告)号：US20110086486A1
公开(公告)日：2011-04-14
申请号：US12969977
申请日：2010-12-16
申请人： Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
发明人： Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
IPC分类号： H01L21/768 , H01L21/02 , H01L21/28
CPC分类号： H01L23/528 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/06181 , H01L2224/13009 , H01L2224/16145 , H01L2224/16225 , H01L2224/48145 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012
摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。第一侧壁间隔层形成在互连孔的侧壁上。在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。然后用通孔电极填充互连孔和未切割凹部。去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

75. 发明申请

US20100011807A1 Capacity modulation compressor and air conditioning system having the same 审中-公开
标题翻译：容量调节压缩机和空调系统具有相同的性能
公开(公告)号：US20100011807A1
公开(公告)日：2010-01-21
申请号：US12289769
申请日：2008-11-03
申请人： Hyuk Nam , Kang-Wook Lee , Seung-Hyoung Ha , Geun-Hyoung Lee
发明人： Hyuk Nam , Kang-Wook Lee , Seung-Hyoung Ha , Geun-Hyoung Lee
IPC分类号： F25B1/04 , H02K21/46 , H02P1/44 , F04B17/03 , F04C18/00 , F04C28/18
CPC分类号： F04C23/008 , F01C21/0863 , F04C18/3564 , F04C28/06 , F04C29/0085 , F04C2270/56 , H02K21/46
摘要： Provided is a capacity modulation compressor, comprising: a shell forming a sealed interior space; a compression mechanism, which is positioned inside the shell and modulates a capacity for compressing a working fluid; and an electromotive driving unit, which is positioned inside the shell, includes a stator and a rotor, and drives the compression mechanism; and a shaft for transferring a torque of the electromotive unit to the compression mechanism, the rotor including a rotor core, conductive bars, flux barriers, and permanent magnets, starting running by an induction torque produced due to the presence of the conductive bars, and operating at a synchronous speed by a reluctance torque produced due to the presence of the flux barriers and a magnetic torque produced to the permanent magnets, and the compressing capacity for the compression mechanism to compress the working fluid being set lower than a maximum compression capacity.
摘要翻译：提供一种容量调节压缩机，包括：壳体，形成密封的内部空间; 压缩机构，其位于壳体内并调制用于压缩工作流体的能力; 并且位于壳体内的电动驱动单元包括定子和转子，并驱动压缩机构; 以及用于将所述电动单元的扭矩传递到所述压缩机构的轴，所述转子包括转子芯，导电棒，磁通屏障和永磁体，由于导电棒的存在而产生的感应转矩开始运行;以及由于存在磁通屏障产生的磁阻转矩和向永久磁铁产生的磁转矩而产生的磁阻转矩以及压缩机构压缩工作流体的压缩能力低于最大压缩容量的同步转速。

76. 发明申请

US20080315242A1 System, apparatus and method of selective laser repair for metal bumps of semiconductor device stack 有权
标题翻译：用于半导体器件堆叠金属凸块的选择性激光修复的系统，设备和方法
公开(公告)号：US20080315242A1
公开(公告)日：2008-12-25
申请号：US12222648
申请日：2008-08-13
申请人： Kang-Wook Lee , Se-Young Jeong
发明人： Kang-Wook Lee , Se-Young Jeong
IPC分类号： H01L29/24 , H01L33/00
CPC分类号： H01L21/485 , B23K26/351 , H01L2224/16145 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump.
摘要翻译：选择性激光修复装置和方法的示例性实施例可以允许通过将激光束施加到损坏和/或缺陷凸起来修复半导体器件堆叠中的金属凸块。可以修复金属凸块，并且不需要分离形成器件堆叠的各个芯片和/或封装。控制单元和驱动单元的操作可以定位激光单元，使得可以在损坏的和/或有缺陷的金属凸块处照射激光束。 X射线检查单元可以获得有关损坏和/或有缺陷的金属凸块的信息。

77. 发明申请

US20070257350A1 Wafer level stack structure for system-in-package and method thereof 有权
公开(公告)号：US20070257350A1
公开(公告)日：2007-11-08
申请号：US11822630
申请日：2007-07-09
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

78. 发明授权

US07276799B2 Chip stack package and manufacturing method thereof 有权
标题翻译：芯片堆叠封装及其制造方法
公开(公告)号：US07276799B2
公开(公告)日：2007-10-02
申请号：US10890995
申请日：2004-07-15
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
摘要翻译：通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率并提高产量。

79. 发明申请

US20070200216A1 Chip stack package 审中-公开
标题翻译：芯片堆栈封装
公开(公告)号：US20070200216A1
公开(公告)日：2007-08-30
申请号：US11703900
申请日：2006-12-19
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
IPC分类号： H01L23/02
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.
摘要翻译：提供了一种芯片堆叠封装，其可以包括下半导体芯片，堆叠在下半导体芯片上的上半导体芯片，以及形成在下半导体芯片和上半导体芯片之间的空间中的至少一个粘合剂。所述至少一种粘合剂可以包括第一粘合剂和第二粘合剂。第一粘合剂可以形成在空间的一部分中，并且第二粘合剂可以形成在除了设置第一粘合剂的区域之外的空间中。相邻的半导体芯片之间的空间可以被至少一个粘合剂完全填充。因此，根据本发明的示例性实施例的芯片堆叠封装可以表现出改进的机械稳定性和可靠性。

80. 发明授权

US07215033B2 Wafer level stack structure for system-in-package and method thereof 有权
标题翻译：用于系统级封装的晶圆级堆叠结构及其方法
公开(公告)号：US07215033B2
公开(公告)日：2007-05-08
申请号：US10899175
申请日：2004-07-27
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
摘要翻译：一种晶片级堆叠结构，包括包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，第二晶片包括至少一个第二芯片尺寸小于第一芯片尺寸的第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，其中所述第一晶片并且第二晶片被堆叠，并且其中第一晶片和第二晶片彼此耦合。一种形成晶片级堆叠结构的方法，包括形成包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，形成第二晶片，其包括小于第一芯片尺寸的第二芯片尺寸的至少一个第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，堆叠第一晶片和第二晶片，并且将第一晶片和第二晶片彼此耦合。一种系统级封装，包括晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的至少一个第一器件芯片和至少一个具有第二多个I / O焊盘的第二器件芯片，以及与晶片级堆叠结构连接的公共电路板。

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