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1. 发明授权

US08004848B2 Stack module, card including the stack module, and system including the stack module 有权
标题翻译：堆叠模块，包括堆叠模块的卡，以及包括堆栈模块的系统
公开(公告)号：US08004848B2
公开(公告)日：2011-08-23
申请号：US12126313
申请日：2008-05-23
申请人： Seung-Duk Baek , Mitsuo Umemoto , Kang-Wook Lee
发明人： Seung-Duk Baek , Mitsuo Umemoto , Kang-Wook Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541
摘要： Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.
摘要翻译：提供了通过使用简化的处理以低成本制造的高可靠性堆栈模块，使用堆栈模块的卡和使用堆栈模块的系统。在堆叠模块中，单元基板相对于彼此层叠，并且每个单元基板包括选择端子。第一选择线电连接到设置在奇数层的第一单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。第二选择线电连接到以偶数层布置的第二单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。选择端子设置在第一选择线和第二选择线之间。

2. 发明授权

US07537959B2 Chip stack package and manufacturing method thereof 有权
标题翻译：芯片堆叠封装及其制造方法
公开(公告)号：US07537959B2
公开(公告)日：2009-05-26
申请号：US11889400
申请日：2007-08-13
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/00 , H01L21/26 , H01L21/44 , H01L29/40
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
摘要翻译：通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率并提高产量。

3. 发明申请

US20070281374A1 Chip stack package and manufacturing method thereof 有权
公开(公告)号：US20070281374A1
公开(公告)日：2007-12-06
申请号：US11889400
申请日：2007-08-13
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/66 , H01L21/58
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

4. 发明授权

US08368231B2 Chipstack package and manufacturing method thereof 有权
公开(公告)号：US08368231B2
公开(公告)日：2013-02-05
申请号：US13154165
申请日：2011-06-06
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

5. 发明申请

US20110237004A1 CHIPSTACK PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：其包装及其制造方法
公开(公告)号：US20110237004A1
公开(公告)日：2011-09-29
申请号：US13154165
申请日：2011-06-06
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/66
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.
摘要翻译：用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

6. 发明授权

US07977156B2 Chipstack package and manufacturing method thereof 有权
标题翻译： Chipstack封装及其制造方法
公开(公告)号：US07977156B2
公开(公告)日：2011-07-12
申请号：US12385855
申请日：2009-04-22
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/00 , H01L21/26 , H01L21/44 , H01L29/40
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.
摘要翻译：用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

7. 发明授权

US07276799B2 Chip stack package and manufacturing method thereof 有权
标题翻译：芯片堆叠封装及其制造方法
公开(公告)号：US07276799B2
公开(公告)日：2007-10-02
申请号：US10890995
申请日：2004-07-15
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
摘要翻译：通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率并提高产量。

8. 发明申请

US20050046002A1 Chip stack package and manufacturing method thereof 有权
标题翻译：芯片堆叠封装及其制造方法
公开(公告)号：US20050046002A1
公开(公告)日：2005-03-03
申请号：US10890995
申请日：2004-07-15
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L21/98 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/44 , H01L21/48 , H01L23/02
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
摘要翻译：通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率并提高产量。

9. 发明申请

US20090209063A1 Chipstack package and manufacturing method thereof 有权
标题翻译： Chipstack封装及其制造方法
公开(公告)号：US20090209063A1
公开(公告)日：2009-08-20
申请号：US12385855
申请日：2009-04-22
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-sik Chung
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.
摘要翻译：用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

10. 再颁专利

USRE45781E1 Toughness, adhesion and smooth metal lines of porous low K dielectric interconnect structures 有权
标题翻译：多孔低K电介质互连结构的韧性，粘附性和光滑的金属线
公开(公告)号：USRE45781E1
公开(公告)日：2015-10-27
申请号：US14176526
申请日：2014-02-10
申请人： Jeffrey C. Hedrick , Kang-Wook Lee , Kelly Malone , Christy S. Tyberg
发明人： Jeffrey C. Hedrick , Kang-Wook Lee , Kelly Malone , Christy S. Tyberg
IPC分类号： H01L21/02 , H01L23/532 , H01L21/70 , H01L23/52 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/22
CPC分类号： H01L21/22 , H01L21/02118 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.
摘要翻译：用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。多层电介质堆叠的固化可以在炉中的单一固化步骤中。多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

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