专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07955893B2 Wafer level chip scale package and process of manufacture 有权
标题翻译：晶圆级芯片级封装及制造工艺
公开(公告)号：US07955893B2
公开(公告)日：2011-06-07
申请号：US12023921
申请日：2008-01-31
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

72. 发明申请

US20110073999A1 MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES AND ITS FABRICATION METHOD 审中-公开
标题翻译：用于包装功率半导体器件的混合合金引线框架及其制造方法
公开(公告)号：US20110073999A1
公开(公告)日：2011-03-31
申请号：US12652881
申请日：2010-01-06
申请人： Zhi Qiang Niu , Jun Lu , Tao Feng
发明人： Zhi Qiang Niu , Jun Lu , Tao Feng
IPC分类号： H01L23/34 , H01L23/495 , H01L21/50
CPC分类号： H01L21/4871 , H01L21/4821 , H01L23/49562 , H01L23/49568 , H01L24/39 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L2224/0603 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/83801 , H01L2224/84801 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.
摘要翻译：本发明公开了一种用于功率半导体器件的混合合金引线框架，其包括多个散热器和引脚阵列; 散热器由第一材料制成，其上部具有定位孔，在其下部中心处具有焊接区，而销阵列由与第一材料不同的第二材料制成，具有多个的端子分别从其上端和下端引出。散热器定位在引线框组件焊接板上，引脚定位在引线框组件焊接板上的上散热器和下散热器之间的区域中。本发明的功率半导体装置用混合合金引线框架，改善了引线框架的散热，降低了引线框架的制造成本，提高了制造的灵活性。

73. 发明授权

US07842543B2 Wafer level chip scale package and method of laser marking the same 有权
标题翻译：晶圆级芯片级封装和激光打标方法相同
公开(公告)号：US07842543B2
公开(公告)日：2010-11-30
申请号：US12378713
申请日：2009-02-17
申请人： Ruisheng Wu , Yan Liu , Tao Feng
发明人： Ruisheng Wu , Yan Liu , Tao Feng
IPC分类号： H01L21/50
CPC分类号： H01L23/544 , H01L21/67282 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/54486 , H01L2224/274 , H01L2924/01079 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091
摘要： A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.
摘要翻译：公开了一种晶片级芯片级封装及其激光标记方法。该方法包括在晶片的前表面上形成多个半导体器件，金属化器件接触晶片的前侧表面，研磨晶片的背面，硅蚀刻晶片的背面，激光标记背面在所述硅蚀刻步骤之后的所述晶片的氧化物，在所述激光标记步骤之后，氧化物蚀刻所述晶片的所述背面，在所述氧化物蚀刻步骤之后，在所述晶片的所述背面表面上沉积金属层，以及将所述晶片切割成晶片级芯片级封装。晶片级芯片级封装包括在其背面形成的标记，该标记包括形成在硅背面中的多个沟槽和形成在覆盖背面金属层中的相应凹痕。

74. 发明申请

US20080182387A1 Method of fabricating a semiconductor device employing electroless plating 有权
标题翻译：使用化学镀的半导体器件的制造方法
公开(公告)号：US20080182387A1
公开(公告)日：2008-07-31
申请号：US11701561
申请日：2007-01-31
申请人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
发明人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
IPC分类号： H01L21/00
CPC分类号： H01L21/67132 , H01L21/288 , H01L21/6836 , H01L24/02 , H01L24/11 , H01L2221/68327 , H01L2224/0401 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014
摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.
摘要翻译：公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取从保护胶带上取下模具。

75. 发明申请

US20080178099A1 Method of using block diagram to combine logic expressions 审中-公开
标题翻译：使用框图组合逻辑表达式的方法
公开(公告)号：US20080178099A1
公开(公告)日：2008-07-24
申请号：US11624217
申请日：2007-01-18
申请人： Tao Feng
发明人： Tao Feng
IPC分类号： G06F3/048
CPC分类号： G06F8/34
摘要： A complicated logic expression uses 4 operators “and”, “or”, “not” and “( )” to combine simpler logic expressions. A method is provided to use lines and blocks to represent these operators and separate the logic expressions.
摘要翻译：复杂的逻辑表达式使用4个运算符“和”，“或”，“not”和“（）”组合更简单的逻辑表达式。提供了一种使用线和块来表示这些运算符并分离逻辑表达式的方法。

76. 发明申请

US20080166837A1 Power MOSFET wafer level chip-scale package 审中-公开
标题翻译：功率MOSFET晶圆级芯片级封装
公开(公告)号：US20080166837A1
公开(公告)日：2008-07-10
申请号：US11652385
申请日：2007-01-10
申请人： Tao Feng , Ming Sun
发明人： Tao Feng , Ming Sun
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/11334 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13091 , H01L2924/00014 , H01L2924/013
摘要： A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. In an alternative embodiment, the method includes the steps of providing a permanent protective layer on a wafer backside, electroless plating a plurality of contact pads on a wafer front side, and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies.
摘要翻译：公开了功率MOSFET晶片级芯片级封装方法。该方法包括在将晶片切割成多个功率MOSFET管芯之前，在晶片正面侧上化学镀电晶片背面和多个接触焊盘并在镀覆的多个接触焊盘上形成焊球。在替代实施例中，该方法包括以下步骤：在晶片背面上提供永久性保护层，在晶片正面侧面化学镀覆多个接触焊盘，以及在将晶片切割成晶片之前在镀覆的多个接触焊盘上形成焊球多个功率MOSFET管芯。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式