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71. 发明申请

US20070246770A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070246770A1
公开(公告)日：2007-10-25
申请号：US11768378
申请日：2007-06-26
申请人： Kazutoshi NAKAMURA , Syotaro Ono
发明人： Kazutoshi NAKAMURA , Syotaro Ono
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42372 , H01L29/42376 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A semiconductor device, including a semiconductor region of the first conduction type which is formed on a semiconductor substrate; a gate electrode at least part of which is present within a trench which is selectively formed in part of the semiconductor region, and an extended top end portion of which is formed to have a wide width via a stepped portion; a gate insulating film which is formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second conduction type which is provided on the semiconductor region via the gate insulating film so as to enclose a side wall except a bottom portion of the trench; a source region of the first conduction type which is formed adjacent to the gate insulating film outside the trench in the vicinity of a top surface of the base layer; and an insulating film which is formed at least partially between a bottom surface of the top end portion and a top surface of the source region and which is formed so as to have a film thickness larger than the film thickness of the gate insulating film within the trench, in which the top end portion is extended from the trench of the gate electrode and formed to have a wider width than the width within the trench via the stepped portion.
摘要翻译：一种半导体器件，包括形成在半导体衬底上的第一导电类型的半导体区域; 栅电极，其至少一部分存在于在半导体区域的一部分中选择性地形成的沟槽中，并且其延伸的顶端部经由阶梯部形成为宽宽度; 栅极绝缘膜，沿沟槽的壁表面形成在沟槽和栅电极之间; 第二导电类型的基极层，其经由栅极绝缘膜设置在半导体区域上，以围绕除了沟槽的底部之外的侧壁; 所述第一导电类型的源极区域在所述基极层的顶表面附近与所述沟槽外部的所述栅极绝缘膜相邻形成; 以及绝缘膜，其至少部分地形成在所述顶端部的底面和所述源极区域的顶面之间，并且形成为具有大于所述栅极绝缘膜的膜厚度的膜厚度沟槽，其中顶端部分从栅电极的沟槽延伸并且形成为具有比沟槽内的经由阶梯部分的宽度更宽的宽度。

72. 发明申请

US20070001194A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070001194A1
公开(公告)日：2007-01-04
申请号：US11476595
申请日：2006-06-29
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/74
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7806 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a pillar layer including first semiconductor pillars of a first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately. The first and second semiconductor pillars include a plurality of diffusion layers formed in a third semiconductor layer as coupled along the depth. The diffusion layers have lateral widths varied at certain periods along the depth. An average of the lateral widths of the diffusion layers in one certain period is made almost equal to another between different periods.
摘要翻译：半导体器件包括：柱层，其包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱，所述第二导电类型横向，周期性地和交替地形成。第一和第二半导体柱包括沿着深度耦合形成在第三半导体层中的多个扩散层。扩散层的横向宽度在沿深度的某些周期变化。在一定时间段内扩散层的横向宽度的平均值在不同周期之间几乎等于另一个。

73. 发明授权

US06693338B2 Power semiconductor device having RESURF layer 有权
标题翻译：具有RESURF层的功率半导体器件
公开(公告)号：US06693338B2
公开(公告)日：2004-02-17
申请号：US10163651
申请日：2002-06-07
申请人： Wataru Saitoh , Ichiro Omura , Masakazu Yamaguchi , Satoshi Aida , Syotaro Ono
发明人： Wataru Saitoh , Ichiro Omura , Masakazu Yamaguchi , Satoshi Aida , Syotaro Ono
IPC分类号： H01L2358
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/3247 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.
摘要翻译：半导体器件包括漏极层，第一和第二漂移层，RESURF层，漏极，基极层，源极层，源极和栅电极。第一漂移层形成在漏极层上。第二漂移层和RESURF层形成在第一漂移层上并且沿与深度方向垂直的方向周期性地布置。 RESURF层通过包括第二漂移层和RESURF层的p-n结在第二漂移层中形成耗尽层。第一漂移层中的杂质浓度不同于第二漂移层中的杂质浓度。漏电极与漏极层电连接。

74. 发明授权

US08716789B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08716789B2
公开(公告)日：2014-05-06
申请号：US13610532
申请日：2012-09-11
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
摘要翻译：根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。该装置包括第一沟槽和第一绝缘膜。第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。第一绝缘膜设置在第一沟槽的侧表面和底表面上。

75. 发明申请

US20130221426A1 ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：电力半导体器件及其制造方法
公开(公告)号：US20130221426A1
公开(公告)日：2013-08-29
申请号：US13600616
申请日：2012-08-31
申请人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
发明人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66719 , H01L29/7802 , H01L29/7811
摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.
摘要翻译：电力半导体装置的制造方法包括以下处理。在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。在外延层的表面形成多个第二第二导电型杂质注入层。在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

76. 发明授权

US08487374B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08487374B2
公开(公告)日：2013-07-16
申请号：US13234802
申请日：2011-09-16
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune , Wataru Saito , Syotaro Ono
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune , Wataru Saito , Syotaro Ono
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42356 , H01L29/42372 , H01L29/7811 , H01L29/7813
摘要： In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.
摘要翻译：通常，根据一个实施例，功率半导体器件包括在第一半导体层上的第一导电类型的第一柱状区域，第二柱状区域和外延层。第一支柱区域由第一导电类型的多个第一支柱层和沿第一方向交替布置的第一导电类型的多个第二支柱层组成。第二柱状区域沿着第一方向与第一柱状区域相邻，并且具有第二导电型的第三柱状层，第一导电型的第四柱状层和第二导电型的第五柱状层沿着第一个方向。多个第二导电类型的第二基极层分别电连接到第三柱层和第五柱层上并彼此间隔开。

77. 发明申请

US20120217555A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120217555A1
公开(公告)日：2012-08-30
申请号：US13357381
申请日：2012-01-24
申请人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/772
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/42356 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7395
摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
摘要翻译：实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。第二控制电极的电阻高于第三控制电极的电阻。

78. 发明授权

US08232593B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08232593B2
公开(公告)日：2012-07-31
申请号：US12714002
申请日：2010-02-26
申请人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/7395 , H01L29/861 , H01L29/8611
摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.
摘要翻译：根据本发明实施例的功率半导体器件包括第一或第二导电类型的第一半导体层，形成在第一半导体层上的第一导电类型的第二半导体层，第二导电类型的第三半导体层选择性地形成在第二半导体层的表面上，形成在第二半导体层的表面上的第三半导体层的周边中的至少一个沟槽，至少一个沟槽的底表面的深度比底部表面，并且比第一半导体层的顶表面浅，并且至少一个沟槽的一些或全部与第三半导体层的侧表面接触，至少一个绝缘体埋在第三半导体层至少一个沟槽，与第一半导体层电连接的第一主电极和电连接的第二主电极引导到第三半导体层。

79. 发明授权

US08159023B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08159023B2
公开(公告)日：2012-04-17
申请号：US12692527
申请日：2010-01-22
申请人： Syotaro Ono , Wataru Saito , Nana Hatano , Hiroshi Ohta , Miho Watanabe
发明人： Syotaro Ono , Wataru Saito , Nana Hatano , Hiroshi Ohta , Miho Watanabe
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712 , H01L29/7397
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，半导体衬底上的第一导电类型的第一半导体区域和分开设置在第一半导体区域中的多个第二导电类型的第二半导体区域。由半导体衬底的表面方向上的第二半导体区域中的净活化掺杂浓度的积分值表示的电荷量与由第一半导体区域中的净活化掺杂浓度的积分值表示的电荷量之间的差异在半导体基板的表面方向总是为正量，并且从第一接合面的深度到与第一接合面相反的一侧的第二接合面的深度变得更大。

80. 发明授权

US08125023B2 Vertical type power semiconductor device having a super junction structure 有权
标题翻译：具有超结结构的垂直型功率半导体器件
公开(公告)号：US08125023B2
公开(公告)日：2012-02-28
申请号：US12620045
申请日：2009-11-17
申请人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7395 , H01L29/7811 , Y10S257/901
摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.
摘要翻译：在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。这允许减小超结结构区域的外周表面上的电场。因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

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