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71. 发明授权

US06831363B2 Structure and method for reducing thermo-mechanical stress in stacked vias 有权
标题翻译：用于降低堆叠过孔中热机械应力的结构和方法
公开(公告)号：US06831363B2
公开(公告)日：2004-12-14
申请号：US10319032
申请日：2002-12-12
申请人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76831 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.
摘要翻译：用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

72. 发明授权

US06700161B2 Variable resistor structure and method for forming and programming a variable resistor for electronic circuits 失效
标题翻译：用于形成和编程用于电子电路的可变电阻器的可变电阻器结构和方法
公开(公告)号：US06700161B2
公开(公告)日：2004-03-02
申请号：US10146072
申请日：2002-05-16
申请人： Louis Lu-Chen Hsu , Chandrasekhar Narayan , Carl J. Radens
发明人： Louis Lu-Chen Hsu , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2973
CPC分类号： H01L23/5254 , H01L23/5252 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable element by either providing a current flow through the programmable element, or directing a laser beam onto the programmable element. The conductive materials are interdiffused to form an alloy of the conductive materials. A resistance value of the variable resistor is determined, at least in part, by the degree to which the conductive materials are alloyed or interdiffused. The method and structure of the variable resistor prevents ablative damage to adjoining circuit structure, allowing tighter pitch, and has application to digital programmable elements, and to resistance trimming for impedance matching in RF integrated circuits.
摘要翻译：用于形成可变电阻器的非烧蚀结构和方法包括提供包括两个或多个不同导电材料的可编程电阻元件，并且通过加热可编程元件来提供可编程电阻元件的电流来改变可编程电阻元件的有限值，通过可编程元件，或将激光束引导到可编程元件上。导电材料相互扩散以形成导电材料的合金。可变电阻器的电阻值至少部分地由导电材料合金化或相互扩散的程度决定。可变电阻器的方法和结构防止邻接电路结构的烧蚀损坏，使得更紧密的间距，并且应用于数字可编程元件，以及用于RF集成电路中的阻抗匹配的电阻调整。

73. 发明授权

US06624499B2 System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient 有权
标题翻译：通过产生温度梯度增强硅化物电迁移来编程熔丝结构的系统
公开(公告)号：US06624499B2
公开(公告)日：2003-09-23
申请号：US10247415
申请日：2002-09-19
申请人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
发明人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.
摘要翻译：本发明提供一种通过电迁移编程的系统，装置和方法。包括阴极和由具有诸如硅化物之类的导电部件的熔丝连接的阳极的半导体熔丝被耦合到电源。电势通过阴极和阳极施加在导电熔丝连接上，其中电位为大小以引发硅化物从半导体熔丝的区域的电迁移，从而降低熔丝链的导电性。响应于所施加的电位，通过实现熔丝链和阴极和阳极中的一个之间的温度梯度来增强电迁移。半导体保险丝的一部分以热传递关系被选择性地冷却以增加温度梯度。在一个实施例中，将散热器施加到阴极。散热器可以是在与熔丝连接绝缘的情况下紧邻阴极耦合的金属层。在另一个实施方案中，通过选择性地改变下面的氧化物层的厚度使得阴极设置在比熔丝链更薄的氧化物层上来增加温度梯度。

74. 发明授权

US06268638B1 Metal wire fuse structure with cavity 失效
标题翻译：金属线熔丝结构带腔
公开(公告)号：US06268638B1
公开(公告)日：2001-07-31
申请号：US09258563
申请日：1999-02-26
申请人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
发明人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2702
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译：集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。

75. 发明授权

US06266272B1 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells 有权
标题翻译：由用作DRAM单元和EPROM单元的多个单晶体管单元形成的部分非易失性动态随机存取存储器
公开(公告)号：US06266272B1
公开(公告)日：2001-07-24
申请号：US09364841
申请日：1999-07-30
申请人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
发明人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
IPC分类号： G11C1450
CPC分类号： G11C16/02 , G11C11/005
摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.
摘要翻译：部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。电池可电可编程为非易失性存储器。这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

76. 发明授权

US6081021A Conductor-insulator-conductor structure 失效
标题翻译：导体 - 绝缘体导体结构
公开(公告)号：US6081021A
公开(公告)日：2000-06-27
申请号：US7889
申请日：1998-01-15
申请人： Jeffrey P. Gambino , Chandrasekhar Narayan , Toshiaki Kirihata
发明人： Jeffrey P. Gambino , Chandrasekhar Narayan , Toshiaki Kirihata
IPC分类号： H01L21/02 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/00
CPC分类号： H01L28/40 , H01L21/76807 , H01L21/76831 , H01L21/76838 , H01L21/76885 , H01L23/5252 , H01L28/60 , H01L21/31612 , H01L21/3185 , H01L2924/0002
摘要： An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.
摘要翻译：一种包括导体 - 绝缘体 - 导体结构的集成电路器件以及同时形成双重镶嵌通孔同时制造该结构的方法。第一互连层形成在第一层间电介质上。开口延伸穿过第二层间介质到第一互连层。绝缘体沉积在开口中。然后将沟槽蚀刻到将成为通孔的开口的上部中，同时从将成为通孔的开口的底部移除绝缘体。然后将导体沉积在开口中并在沟槽中，并使用化学机械抛光（CMP）来对导体进行图案化。然后沉积第三层间电介质，形成延伸到导体的开口，并且沉积和图案化第三互连层导体。

77. 发明授权

US5818563A Substrate structure and assembly method for reduced spatial light modulator size 失效
标题翻译：降低空间光调制器尺寸的基板结构和组装方法
公开(公告)号：US5818563A
公开(公告)日：1998-10-06
申请号：US926152
申请日：1997-09-09
申请人： Evan George Colgan , Robert Lee Melcher , Teruhiro Nakasogi , Chandrasekhar Narayan , James Lawrence Sanford , Kei-Hsiung Yang
发明人： Evan George Colgan , Robert Lee Melcher , Teruhiro Nakasogi , Chandrasekhar Narayan , James Lawrence Sanford , Kei-Hsiung Yang
IPC分类号： G02F1/1339 , G02F1/136 , G02F1/1345 , G02F1/13 , G02F1/1333
CPC分类号： G02F1/136 , G02F1/1339
摘要： A spatial light modulator designed to use a minimum area on the surface of a silicon substrate. This invention comprises a silicon substrate on a back plate with a glass cover that is used to seal liquid crystal between the glass cover and the silicon substrate. Most importantly, the glue seal formed to contain the liquid crystal material is between the cover glass plate and the Si substrate on only one side and the back plate on the remaining three sides. This structure allows a smaller semiconductor substrate to be used.
摘要翻译：设计用于在硅衬底的表面上使用最小面积的空间光调制器。本发明包括在背板上的硅衬底，其具有用于密封玻璃盖和硅衬底之间的液晶的玻璃盖。最重要的是，形成为容纳液晶材料的胶合密封件仅在一侧的盖玻璃板和Si基板之间，其余三侧上的背板之间。这种结构允许使用较小的半导体衬底。

78. 发明授权

US5721602A Mechanical packaging and thermal management of flat mirror arrays 失效
标题翻译：平面镜阵列的机械包装和热管理
公开(公告)号：US5721602A
公开(公告)日：1998-02-24
申请号：US540860
申请日：1995-10-11
申请人： Chandrasekhar Narayan , Evan Colgan , Kei-Hsiung Yang , Robert L. Melcher , Lawrence S. Mok , Leathen Shi , Thomas M. Cipolla
发明人： Chandrasekhar Narayan , Evan Colgan , Kei-Hsiung Yang , Robert L. Melcher , Lawrence S. Mok , Leathen Shi , Thomas M. Cipolla
IPC分类号： G02F1/13 , G02F1/133 , G02F1/1333 , G02F1/136 , G09F9/00 , H04N5/74
CPC分类号： G02F1/133385 , G02F1/133308 , G02F1/136 , G02F2001/133322 , G02F2001/133325
摘要： A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.
摘要翻译：提供液晶元件，提供热和对准控制的封装结构，包括该液晶元件的显示装置，以及制造和组装方法。液晶元件包括：具有微电路的半导体晶片和反射像素阵列; 设置在反射像素上的均匀厚度的电光响应液晶介质层; 位于液晶上的透明导电层基本上平行于反射层，以确保液晶的均匀厚度; 以及设置在导电层上的绝缘透明层。将液晶元件层压到光学平面基板上以限制其平面外失真。由元件和基板形成的结构设置在安装到布线板上的基板保持器中，并连接到用于致动液晶的电压源。在安装期间，使用对准夹具来确保元件相对于相关光学元件的正确取向。一旦元件被定位，散热器耦合到衬底保持器的后表面以散热。

79. 发明授权

US5687078A Fine pitch bonding 失效
标题翻译：细间距键合
公开(公告)号：US5687078A
公开(公告)日：1997-11-11
申请号：US476531
申请日：1995-06-07
申请人： Raymond Robert Horton , Chandrasekhar Narayan , Michael Jon Palmer
发明人： Raymond Robert Horton , Chandrasekhar Narayan , Michael Jon Palmer
IPC分类号： H01L21/00 , G01K7/00
CPC分类号： H01L21/67144
摘要： In a bonding station, a tooling principle is provided wherein first and second tool parts respectively hold first and second apparatus parts, each apparatus part having fine conductor periodicity edge bonding regions, in superpositioned registration with the tool parts providing space and accessability for optical alignment and for bonding heat and pressure. The tool members retain a first, position registered, apparatus part, with "X" - "Y" registration capability, in position with an edge bearing a fine conductor periodicity accessable by a tapered edge of the tool which permits optical fine alignment adjustment and bonding heat and pressure application.
摘要翻译：在焊接站中，提供了一种工具原理，其中第一和第二工具部分分别保持第一和第二装置部分，每个装置部分具有精细的导体周期性边缘接合区域，与工具部件重叠对准，为光学对准提供空间和可访问性，用于粘合热和压力。工具构件保持具有“X” - “Y”配准能力的第一位置登记的装置部分，其位置具有可由工具的锥形边缘访问的精细导体周期性的边缘，其允许光学精细对准调整和结合热和压力应用。

80. 发明授权

US5534094A Method for fabricating multi-layer thin film structure having a separation layer 失效
标题翻译：具有分离层的多层薄膜结构的制造方法
公开(公告)号：US5534094A
公开(公告)日：1996-07-09
申请号：US314789
申请日：1994-09-29
申请人： Gnanalingam Arjavalingam , Alina Deutsch , Fuad E. Doany , Bruce K. Furman , Donald J. Hunt , Chandrasekhar Narayan , Modest M. Oprysko , Sampath Purushothaman , Vincent Ranieri , Stephen Renick , Jane M. Shaw , Janusz S. Wilczynski , David F. Witman
发明人： Gnanalingam Arjavalingam , Alina Deutsch , Fuad E. Doany , Bruce K. Furman , Donald J. Hunt , Chandrasekhar Narayan , Modest M. Oprysko , Sampath Purushothaman , Vincent Ranieri , Stephen Renick , Jane M. Shaw , Janusz S. Wilczynski , David F. Witman
IPC分类号： B23K26/00 , B32B37/00 , H01L21/68 , H01L23/12 , H01L23/15 , H05K3/00 , H05K3/46 , B32B31/28
CPC分类号： H01L21/6835 , H01L2221/68345 , H01L2221/68359 , H05K3/0011 , H05K3/46 , Y10T156/1158 , Y10T428/12528 , Y10T428/12549 , Y10T428/12569 , Y10T428/12611
摘要： A method and apparatus for releasing a workpiece from a substrate including providing a substrate which is transparent to a predetermined wavelength of electromagnetic radiation; forming, on the substrate, a separation layer which degrades in response to the predetermined radiation; providing the workpiece on the separation layer; and directing the predetermined radiation at the separation layer through the transparent substrate so as to degrade the separation layer and to separate the workpiece from the substrate.
摘要翻译：一种用于从衬底释放工件的方法和装置，包括提供对预定波长的电磁辐射是透明的衬底; 在衬底上形成响应于预定辐射而降解的分离层; 在分离层上提供工件; 并且通过透明基板将分离层处的预定辐射引导，以使分离层退化并将工件与基板分离。

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