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71. 发明授权

US07566971B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07566971B2
公开(公告)日：2009-07-28
申请号：US11417187
申请日：2006-05-04
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： H01L29/40 , H01L21/4763
CPC分类号： H01L23/5225 , H01L23/552 , H01L27/124 , H01L27/13 , H01L29/78624 , H01L29/78633 , H01L2223/6677 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has a first conductive layer over a first insulating layer; a second insulating layer over the first conductive layer, which includes an opening extending to the first conductive layer; and a signal wiring layer for electrically connecting an integrated circuit portion to an antenna and a second conductive layer adjacent to the signal wiring layer, which are formed over the second insulating layer. The second conductive layer is in contact with the first conductive layer through the opening, and the first conductive layer overlaps the signal wiring layer with the second insulating layer interposed therebetween.
摘要翻译：本发明提供了以低成本和高产率制造更高性能和更高可靠性的半导体器件的技术。本发明的半导体器件在第一绝缘层上具有第一导电层; 在第一导电层上的第二绝缘层，其包括延伸到第一导电层的开口; 以及用于将集成电路部分电连接到天线的信号布线层和与所述信号布线层相邻的第二导电层，所述第二导电层形成在所述第二绝缘层上。第二导电层通过开口与第一导电层接触，并且第一导电层与信号布线层重叠，其间插入第二绝缘层。

72. 发明申请

US20050240930A1 Parallel processing computer 失效
标题翻译：并行处理电脑
公开(公告)号：US20050240930A1
公开(公告)日：2005-10-27
申请号：US10992675
申请日：2004-11-22
申请人： Makoto Amamiya , Satoshi Amamiya , Takanori Matsuzaki
发明人： Makoto Amamiya , Satoshi Amamiya , Takanori Matsuzaki
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/3012 , G06F9/30123 , G06F9/461 , G06F9/485 , G06F9/4881
摘要： There is provided a parallel processing computer for executing a plurality of threads concurrently and in parallel. The computer includes: a thread activation controller for determining whether or not each of threads, which are exclusively executable program fragments, is ready-to-run, to put the thread determined ready-to-run into a ready thread queue as ready-to-run thread; and a thread execution controller having a pre-load unit, an EU allocation and trigger unit, a plurality of thread execution units and a plurality of register files including a plurality of registers, and the pre-load unit, prior to when each ready-to-run thread in the ready thread queue is executed, allocates a free register file of the plurality of register files to the each ready-to-run thread, to load initial data for the each ready-to-run thread into the allocated register file, and the EU allocation and trigger unit, when there is a thread execution unit in idle state of the plurality of thread execution unit, retrieves ready-to-run thread from the top of the ready thread queue, and to allocate the retrieved ready-to-run thread to the thread execution unit in idle state, and to couple the register file loaded the initial data for the ready-to-run thread with the allocated thread execution unit in idle state, and to trigger the ready-to-run thread. The plurality of thread execution units execute the triggered threads concurrently in parallel.
摘要翻译：提供了并行处理计算机，并行并行地执行多个线程。该计算机包括：线程激活控制器，用于确定每一个是唯一可执行程序片段的线程是否准备好运行，以便将所确定的线程准备好运行到准备好的线程队列中，润滑线以及具有预加载单元，EU分配和触发单元，多个线程执行单元和包括多个寄存器的多个寄存器文件以及预加载单元的线程执行控制器，执行就绪线程队列中的运行线程，将多个寄存器文件的空闲寄存器文件分配给每个即将发送的线程，以将每个准备运行的线程的初始数据加载到分配的寄存器中文件和EU分配和触发单元，当多个线程执行单元处于空闲状态的线程执行单元时，从准备线程队列的顶部检索准备运行的线程，并且分配所检索的准备在线程执行单元处于空闲状态，并将寄存器文件耦合到备用线程的初始数据与处于空闲状态的分配的线程执行单元，并且触发即时运行线程，运行线程。多个线程执行单元并行执行触发的线程。

73. 发明授权

US06173334B2 Network system including a plurality of lan systems and an intermediate network having independent address schemes 失效
标题翻译：包括多个lan系统的网络系统和具有独立地址方案的中间网络
公开(公告)号：US06173334B2
公开(公告)日：2001-01-09
申请号：US09166860
申请日：1998-10-06
申请人： Takanori Matsuzaki , Hiroshi Sakurai
发明人： Takanori Matsuzaki , Hiroshi Sakurai
IPC分类号： G06F1300
CPC分类号： H04L29/12367 , H04L12/4604 , H04L29/12009 , H04L29/12424 , H04L61/2514 , H04L61/2535
摘要： A network system is constructed by: a first LAN system having first terminal equipment; a second LAN system having second terminal equipment; an intermediate network to connect the first and second LAN systems; first communication equipment to transfer a packet between the first LAN system and the intermediate network; and second communication equipment to transfer a packet between the second LAN system and the intermediate network. To transfer the packet from the first terminal equipment to the second terminal equipment, the first communication equipment converts an address showing a transmission destination of the packet transmitted from the first terminal equipment from an address defined on the first LAN system to an address defined on the intermediate network and transfers the converted address from the first LAN system to the intermediate network. The second communication equipment converts an address showing the transmission destination of the packet on the intermediate network from the address defined on the intermediate network to an address defined on the second LAN system and transfers the converted address from the intermediate network to the second LAN system.
摘要翻译：网络系统由以下部分构成：具有第一终端设备的第一LAN系统; 具有第二终端设备的第二LAN系统; 连接第一和第二LAN系统的中间网络; 第一通信设备，用于在第一LAN系统和中间网络之间传送分组; 以及用于在第二LAN系统和中间网络之间传送分组的第二通信设备。为了将分组从第一终端设备传送到第二终端设备，第一通信设备将表示从第一终端设备发送的分组的发送目的地的地址从在第一LAN系统上定义的地址转换为并将转换的地址从第一LAN系统传送到中间网络。第二通信设备将表示中间网络上的分组的发送目的地的地址从中间网络上定义的地址转换为在第二LAN系统上定义的地址，并将转换的地址从中间网络传送到第二LAN系统。

74. 发明授权

US08264874B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08264874B2
公开(公告)日：2012-09-11
申请号：US12890856
申请日：2010-09-27
申请人： Toshihiko Saito , Takanori Matsuzaki
发明人： Toshihiko Saito , Takanori Matsuzaki
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C17/16 , G11C2213/33 , G11C2213/34 , G11C2213/79 , H01L27/24
摘要： Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included in the semiconductor device are formed of the same material. Therefore, the memory layer and the resistive layer are formed in the same step, whereby the number of manufacturing steps of the semiconductor device can be reduced. As a result, the manufacturing yield of the semiconductor devices can be improved and the manufacturing cost can be reduced. In addition, the semiconductor device includes a resistor having a resistive component which has high resistance value. Consequently, the area of the integrated circuit included in the semiconductor device can be reduced.
摘要翻译：本发明的目的是提高半导体器件的制造成品率，降低半导体器件的制造成本，并且减小包括在半导体器件中的集成电路的电路面积。存储元件的存储层和包含在半导体器件中的电阻器的电阻层由相同的材料形成。因此，在相同的步骤中形成存储层和电阻层，从而可以减少半导体器件的制造步骤的数量。结果，可以提高半导体器件的制造成品率，并且可以降低制造成本。此外，半导体器件包括具有高电阻值的电阻元件的电阻器。因此，可以减少包括在半导体器件中的集成电路的面积。

75. 发明授权

US07978787B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07978787B2
公开(公告)日：2011-07-12
申请号：US11914601
申请日：2006-05-25
申请人： Yutaka Shionoiri , Takanori Matsuzaki
发明人： Yutaka Shionoiri , Takanori Matsuzaki
IPC分类号： H04L27/00 , H03K9/00
CPC分类号： H01L27/1266 , G06K19/0723 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L29/41733
摘要： It is an object of the present invention to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width in a semiconductor device capable of communicating data wirelessly. In a semiconductor device, a level shift circuit is provided between a data demodulation circuit and each circuit block where demodulated signals are outputted from the data demodulation circuit. In such a manner, voltage amplitude of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, a pulse width of the demodulated signal is made almost equal to that of signals in each circuit block, or a pulse width of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, it is possible to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width.
摘要翻译：本发明的目的是防止由于能够无线地传送数据的半导体装置中的脉冲宽度的差异而导致的诸如无响应的错误或故障。在半导体装置中，在数据解调电路和解调信号从数据解调电路输出的每个电路块之间提供电平移位电路。以这种方式，解调信号的电压幅度几乎等于来自每个电路块的输出信号的电压振幅。因此，解调信号的脉冲宽度大致等于每个电路块中的信号的脉冲宽度，或者使解调信号的脉冲宽度与来自每个电路块的输出信号的脉冲宽度相等。因此，可以防止由于脉冲宽度的差异而引起的诸如无响应的错误或故障。

76. 发明授权

US07650602B2 Parallel processing computer 失效
标题翻译：并行处理电脑
公开(公告)号：US07650602B2
公开(公告)日：2010-01-19
申请号：US10992675
申请日：2004-11-22
申请人： Makoto Amamiya , Satoshi Amamiya , Takanori Matsuzaki
发明人： Makoto Amamiya , Satoshi Amamiya , Takanori Matsuzaki
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/3012 , G06F9/30123 , G06F9/461 , G06F9/485 , G06F9/4881
摘要： There is provided a parallel processing computer for executing a plurality of threads concurrently and in parallel. The computer includes: a thread activation controller for determining whether or not each of threads, which are exclusively executable program fragments, is ready-to-run, to put the thread determined ready-to-run into a ready thread queue as ready-to-run thread; and a thread execution controller having a pre-load unit, an EU allocation and trigger unit, a plurality of thread execution units and a plurality of register files including a plurality of registers, and the pre-load unit, prior to when each ready-to-run thread in the ready thread queue is executed, allocates a free register file of the plurality of register files to the each ready-to-run thread, to load initial data for the each ready-to-run thread into the allocated register file, and the EU allocation and trigger unit, when there is a thread execution unit in idle state of the plurality of thread execution unit, retrieves ready-to-run thread from the top of the ready thread queue, and to allocate the retrieved ready-to-run thread to the thread execution unit in idle state, and to couple the register file loaded the initial data for the ready-to-run thread with the allocated thread execution unit in idle state, and to trigger the ready-to-run thread. The plurality of thread execution units execute the triggered threads concurrently in parallel.
摘要翻译：提供了并行处理计算机，并行并行地执行多个线程。该计算机包括：线程激活控制器，用于确定每一个是唯一可执行程序片段的线程是否准备好运行，以便将所确定的线程准备好运行到准备好的线程队列中作为准备就绪润滑线以及具有预加载单元，EU分配和触发单元，多个线程执行单元和包括多个寄存器的多个寄存器文件以及预加载单元的线程执行控制器，执行就绪线程队列中的运行线程，将多个寄存器文件的空闲寄存器文件分配给每个即将发送的线程，以将每个准备运行的线程的初始数据加载到分配的寄存器中文件和EU分配和触发单元，当多个线程执行单元处于空闲状态的线程执行单元时，从准备线程队列的顶部检索准备运行的线程，并且分配所检索的准备在线程执行单元处于空闲状态，并将寄存器文件耦合到备用线程的初始数据与处于空闲状态的分配的线程执行单元，并且触发即时运行线程，运行线程。多个线程执行单元并行执行触发的线程。

77. 发明申请

US20090085638A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20090085638A1
公开(公告)日：2009-04-02
申请号：US11914601
申请日：2006-05-25
申请人： Yutaka Shionoiri , Takanori Matsuzaki
发明人： Yutaka Shionoiri , Takanori Matsuzaki
IPC分类号： H03L5/00
CPC分类号： H01L27/1266 , G06K19/0723 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L29/41733
摘要： It is an object of the present invention to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width in a semiconductor device capable of communicating data wirelessly. In a semiconductor device, a level shift circuit is provided between a data demodulation circuit and each circuit block where demodulated signals are outputted from the data demodulation circuit. In such a manner, voltage amplitude of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, a pulse width of the demodulated signal is made almost equal to that of signals in each circuit block, or a pulse width of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, it is possible to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width.
摘要翻译：本发明的目的是防止由于能够无线地传送数据的半导体装置中的脉冲宽度的差异而导致的诸如无响应的错误或故障。在半导体装置中，在数据解调电路和解调信号从数据解调电路输出的每个电路块之间提供电平移位电路。以这种方式，解调信号的电压幅度几乎等于来自每个电路块的输出信号的电压振幅。因此，解调信号的脉冲宽度大致等于每个电路块中的信号的脉冲宽度，或者使解调信号的脉冲宽度与来自每个电路块的输出信号的脉冲宽度相等。因此，可以防止由于脉冲宽度的差异而引起的诸如无响应的错误或故障。

78. 发明授权

US08929161B2 Signal processing circuit 有权
标题翻译：信号处理电路
公开(公告)号：US08929161B2
公开(公告)日：2015-01-06
申请号：US13446661
申请日：2012-04-13
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C11/404 , G11C16/0416 , H01L27/1156 , H01L27/1225
摘要： A signal processing circuit including a nonvolatile storage circuit with a novel structure. The signal processing circuit includes a circuit that is supplied with a power supply voltage and has a first node to which a first high power supply potential is applied, and a nonvolatile storage circuit for holding a potential of the first node. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer, and a second node that is brought into a floating state when the transistor is turned off. A second high power supply potential or a ground potential is input to a gate of the transistor. When the power supply voltage is not supplied, the ground potential is input to the gate of the transistor and the transistor is kept off. The second high power supply potential is higher than the first high power supply potential.
摘要翻译：一种包括具有新颖结构的非易失性存储电路的信号处理电路。信号处理电路包括被提供有电源电压并具有施加第一高电源电位的第一节点的电路和用于保持第一节点的电位的非易失性存储电路。非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管，以及当晶体管截止时成为浮置状态的第二节点。第二高电源电位或接地电位被输入到晶体管的栅极。当不提供电源电压时，接地电位被输入到晶体管的栅极，并且晶体管保持截止。第二个高电源电位高于第一个高电源电位。

79. 发明授权

US08842459B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08842459B2
公开(公告)日：2014-09-23
申请号：US13489628
申请日：2012-06-06
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： G11C5/06 , H01L27/108 , G11C11/402
CPC分类号： H01L27/108 , G11C11/4023 , H01L27/10894
摘要： A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is electrically connected to a bit line. One terminal of the capacitor is electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor is electrically connected to a wiring. One terminal of one of the resistor and the diode is electrically connected to the other of the source and the drain of the transistor, and the other terminal of one of the resistor and the diode is electrically connected to the wiring.
摘要翻译：提供了包括存储单元的半导体器件。存储单元包括晶体管和电容器，以及电阻器和二极管之一。晶体管的栅极电连接到字线，并且晶体管的源极和漏极中的一个电连接到位线。电容器的一个端子电连接到晶体管的源极和漏极中的另一个，并且电容器的另一个端子电连接到布线。电阻器和二极管中的一个的一个端子电连接到晶体管的源极和漏极中的另一个，并且电阻器和二极管中的一个的另一个端子电连接到布线。

80. 发明授权

US08198936B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08198936B2
公开(公告)日：2012-06-12
申请号：US12753984
申请日：2010-04-05
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： H03D1/10 , H04L27/06 , H04B1/16
CPC分类号： G06K19/07749 , H04L27/06
摘要： A semiconductor device is provided, which comprises a first demodulation circuit, a second demodulation circuit, a first bias circuit, a second bias circuit, a comparator, an analog buffer circuit, and a pulse detection circuit. An input portion of the pulse detection circuit is electrically connected to an output portion of the analog buffer circuit, a first output portion of the pulse detection circuit is electrically connected to an input portion of the first bias circuit, and a second output portion of the pulse detection circuit is electrically connected to an input portion of the second bias circuit.
摘要翻译：提供一种半导体器件，其包括第一解调电路，第二解调电路，第一偏置电路，第二偏置电路，比较器，模拟缓冲电路和脉冲检测电路。脉冲检测电路的输入部分电连接到模拟缓冲电路的输出部分，脉冲检测电路的第一输出部分电连接到第一偏置电路的输入部分，第二输出部分脉冲检测电路电连接到第二偏置电路的输入部分。

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