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71. 发明授权

US07438759B2 Ambient environment nanowire sensor 失效
公开(公告)号：US07438759B2
公开(公告)日：2008-10-21
申请号：US11264113
申请日：2005-11-01
申请人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B1/02
CPC分类号： B81C1/00182 , B81B2201/0214 , Y10S977/712 , Y10S977/762
摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

72. 发明申请

US20080157354A1 Multiple stacked nanostructure arrays and methods for making the same 审中-公开
标题翻译：多层叠纳米结构阵列及其制造方法
公开(公告)号：US20080157354A1
公开(公告)日：2008-07-03
申请号：US11649523
申请日：2007-01-03
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L27/00 , H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , G01N27/127 , H01L29/0673 , H01L29/0676 , H01L31/03529 , Y02E10/50
摘要： A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.
摘要翻译：一种叠层纳米结构阵列的制造方法包括：制备衬底; 直接在基板上形成底部电极; 直接在底部电极上生长第一个纳米结构阵列; 在所述第一纳米结构阵列上形成绝缘层; 暴露第一纳米结构阵列的上表面; 在第二和随后的纳米结构阵列正下方的纳米结构阵列上沉积第二和随后的纳米结构阵列; 重复所述形成，所述曝光和沉积随后的步骤以形成堆叠的纳米结构阵列; 去除最上层绝缘层; 并在最上面的纳米结构阵列上形成顶部电极。结合纳米结构阵列的传感器包括其间具有多层纳米结构阵列的顶部和底部电极。

73. 发明授权

US07364924B2 Silicon phosphor electroluminescence device with nanotip electrode 有权
标题翻译：具有纳米尖电极的硅荧光体电致发光器件
公开(公告)号：US07364924B2
公开(公告)日：2008-04-29
申请号：US11061946
申请日：2005-02-17
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H01L21/00
CPC分类号： H05B33/145
摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
摘要翻译：提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。在一个方面，Si磷光体层是SRSO层。响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

74. 发明授权

US07208372B2 Non-volatile memory resistor cell with nanotip electrode 失效
标题翻译：带纳米尖电极的非易失性存储器电阻单元
公开(公告)号：US07208372B2
公开(公告)日：2007-04-24
申请号：US11039544
申请日：2005-01-19
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H01L21/06 , H01L21/461
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
摘要翻译：提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

75. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

76. 发明授权

US06906366B2 Single transistor ferroelectric transistor structure with high-k insulator 失效
标题翻译：具有高k绝缘体的单晶体管铁电晶体管结构
公开(公告)号：US06906366B2
公开(公告)日：2005-06-14
申请号：US10441661
申请日：2003-05-20
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/3105 , H01L21/316 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/02189 , H01L21/02197 , H01L21/02271 , H01L21/0228 , H01L21/28291 , H01L21/31053 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/66545 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

77. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

78. 发明授权

US08242482B2 Nanotip electrode electroluminescence device 有权
标题翻译：纳米电极电致发光器件
公开(公告)号：US08242482B2
公开(公告)日：2012-08-14
申请号：US12042983
申请日：2008-03-05
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H01L31/072
CPC分类号： H05B33/145
摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
摘要翻译：提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。该方法包括：用纳米尖端形成底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。在一个方面，Si磷光体层是SRSO层。响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

79. 发明申请

US20080197399A1 Nanotip capacitor 失效
标题翻译：纳米电容器
公开(公告)号：US20080197399A1
公开(公告)日：2008-08-21
申请号：US11707712
申请日：2007-02-16
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/94 , B82Y10/00 , H01L28/91 , H01L29/66083
摘要： A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.
摘要翻译：提供了一种纳米尖端电容器和相关联的制造方法。该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

80. 发明申请

US20080096345A1 Nanoelectrochemical cell 失效
标题翻译：纳米电化学电池
公开(公告)号：US20080096345A1
公开(公告)日：2008-04-24
申请号：US11580623
申请日：2006-10-12
申请人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
发明人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
IPC分类号： H01G9/00 , H01L21/8242
CPC分类号： H01G9/07 , Y10S977/762 , Y10T29/417
摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.
摘要翻译：提供了形成纳米电化学（NEC）电池的方法。该方法提供了具有顶部表面的底部电极。形成纳米线贝壳。每个纳米线壳具有纳米线和套管，纳米线连接到底部电极顶表面。顶部电极形成在纳米线壳上。在顶部电极和底部电极之间形成主要腔室，部分地被第一多个纳米线壳体置换。通过蚀刻第一牺牲层，在套筒和纳米线之间形成电解质空腔。在一个方面，在底部电极顶表面和连接套筒底部开口的外壳涂层之间形成电解质腔。然后，主要和电解质空腔填充有液相或气相电解质。在不同的方面，第一牺牲层是不被蚀刻掉的固相电解质。

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