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71. 发明授权

US07129582B2 Reducing the migration of grain boundaries 有权
标题翻译：减少晶界迁移
公开(公告)号：US07129582B2
公开(公告)日：2006-10-31
申请号：US11182929
申请日：2005-07-15
申请人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
发明人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.
摘要翻译：形成半导体器件的方法包括将沉淀注入到至少部分形成的半导体器件的栅极导体中。栅极导体包括多个半导体晶粒。形成掺杂剂迁移路径的相邻晶粒的边界。在栅极导体内形成多个沉淀区。位于至少两个晶粒的结的至少一些沉淀区域。至少部分形成的半导体器件的栅极导体掺杂有掺杂剂。掺杂剂沿掺杂剂迁移路径向内扩散。

72. 发明申请

US20060040462A1 Novel method to improve SRAM performance and stability 有权
标题翻译：提高SRAM性能和稳定性的新方法
公开(公告)号：US20060040462A1
公开(公告)日：2006-02-23
申请号：US10921532
申请日：2004-08-19
申请人： Zhiqiang Wu , Shaofeng Yu , C. Cleavelin
发明人： Zhiqiang Wu , Shaofeng Yu , C. Cleavelin
IPC分类号： H01L21/76
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11
摘要： A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.
摘要翻译：公开了一种用于增加晶体管（300）的宽度的技术，同时可以缩小晶体管本身。通过在与晶体管（300）相邻的浅沟槽隔离（STI）区域（328）内形成凹槽（352）来增加晶体管宽度（382）。凹部（352）提供围绕晶体管的区域，从而增加晶体管（300）的宽度（382）。该环绕区域为掺杂剂原子沉积提供了额外的空间，这有助于随机掺杂剂波动（RDF）的减少。以这种方式，根据本发明的一个或多个方面形成的晶体管可以在并入SRAM时产生改善的性能，因为这种晶体管将更加紧密匹配的可能性增加。

73. 发明授权

US06913980B2 Process method of source drain spacer engineering to improve transistor capacitance 有权
标题翻译：源极间隔工程的工艺方法，以提高晶体管电容
公开(公告)号：US06913980B2
公开(公告)日：2005-07-05
申请号：US10609823
申请日：2003-06-30
申请人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
发明人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/2652 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.
摘要翻译：提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。补偿区域比源极和漏极区域稍微间隔开。该间隔影响电位轮廓并降低晶体管内的结电容。通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

74. 发明申请

US20050093032A1 Transistor having a germanium implant region located therein and a method of manufacture therefor 有权
标题翻译：具有锗植入区域的晶体管及其制造方法
公开(公告)号：US20050093032A1
公开(公告)日：2005-05-05
申请号：US10701818
申请日：2003-11-05
申请人： Kaiping Liu , Zhiqiang Wu , Majid Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Mansoorz
IPC分类号： H01L21/265 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/76 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

75. 发明授权

US06885542B2 Capacitor structure 失效
标题翻译：电容结构
公开(公告)号：US06885542B2
公开(公告)日：2005-04-26
申请号：US10932503
申请日：2004-09-02
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/228
CPC分类号： H01L27/10852 , H01L28/82
摘要： A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：电容器形成为具有大致凹入的形状并且具有可选的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

76. 发明授权

US06703690B2 Apparatus for reducing isolation stress in integrated circuits 失效
标题翻译：降低集成电路隔离应力的方法和装置
公开(公告)号：US06703690B2
公开(公告)日：2004-03-09
申请号：US10188472
申请日：2002-07-02
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332
摘要： Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.
摘要翻译：通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。通过改变氮化硅中的硅含量来实现分级。氮化硅可以以基本线性或非线性方式分级。在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。在另一个实施例中，通过在衬底层上形成氮化硅来降低应力，衬底层又形成在基底层上。

77. 发明授权

US06475852B2 Method of forming field effect transistors and related field effect transistor constructions 有权
公开(公告)号：US06475852B2
公开(公告)日：2002-11-05
申请号：US09999886
申请日：2001-10-31
申请人： Zhiqiang Wu , Paul Hatab
发明人： Zhiqiang Wu , Paul Hatab
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/105 , H01L29/41775 , H01L29/66537 , H01L29/66553 , H01L29/66606 , H01L29/7833 , Y10S257/917
摘要： Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

78. 发明授权

US06459116B1 Capacitor structure 有权
公开(公告)号：US06459116B1
公开(公告)日：2002-10-01
申请号：US09283606
申请日：1999-04-01
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

79. 发明授权

US06400002B1 Methods of forming field effect transistors and related field effect transistor constructions 有权
公开(公告)号：US06400002B1
公开(公告)日：2002-06-04
申请号：US09490257
申请日：2000-01-24
申请人： Zhiqiang Wu , Paul Hatab
发明人： Zhiqiang Wu , Paul Hatab
IPC分类号： H01L29207
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/105 , H01L29/41775 , H01L29/66537 , H01L29/66553 , H01L29/66606 , H01L29/7833 , Y10S257/917
摘要： Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

80. 发明授权

US06335234B2 Methods of forming field effect transistors and related field effect transistor constructions 有权
公开(公告)号：US06335234B2
公开(公告)日：2002-01-01
申请号：US09495416
申请日：2000-01-31
申请人： Zhiqiang Wu , Paul Hatab
发明人： Zhiqiang Wu , Paul Hatab
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/105 , H01L29/41775 , H01L29/66537 , H01L29/66553 , H01L29/66606 , H01L29/7833 , Y10S257/917
摘要： Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

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