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71. 发明授权

US6046093A Method of forming capacitors and related integrated circuitry 失效
标题翻译：形成电容器和相关集成电路的方法
公开(公告)号：US6046093A
公开(公告)日：2000-04-04
申请号：US876057
申请日：1997-06-13
申请人： Scott J. DeBoer , Klaus F. Schuegraf , Randhir P. S. Thakur
发明人： Scott J. DeBoer , Klaus F. Schuegraf , Randhir P. S. Thakur
IPC分类号： H01L21/02 , H01L27/108 , H01L21/20
CPC分类号： H01L28/84 , H01L28/91 , H01L27/10811
摘要： Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to be rougher than at least some of the internal container surface. A capacitor dielectric layer and an outer capacitor plate layer are formed over at least portions of the internal and the external surfaces of the capacitor container. In another implementation, a layer comprising roughened polysilicon is formed over at least some of the external container surface but not over any of the internal container surface. In a preferred aspect, the roughened external surface or roughened polysilicon comprises hemispherical grain polysilicon.
摘要翻译：描述了电容器结构及其形成方法。在一个实施方案中，电容器容器形成在衬底上并且包括内表面和外表面。至少一些外表面被提供为比内部容器表面中的至少一些更粗糙。在电容器容器的内表面和外表面的至少一部分上形成电容器介电层和外电容器板层。在另一个实施方案中，包含粗糙多晶硅的层形成在至少一些外部容器表面上，但不在任何内部容器表面上。在优选的方面，粗糙化的外表面或粗糙多晶硅包括半球形晶粒多晶硅。

72. 发明授权

US5994240A Method for cleaning semiconductor wafers 失效
标题翻译：清洗半导体晶圆的方法
公开(公告)号：US5994240A
公开(公告)日：1999-11-30
申请号：US915517
申请日：1997-08-13
申请人： Randhir P. S. Thakur
发明人： Randhir P. S. Thakur
IPC分类号： C23C16/44 , H01L21/31
CPC分类号： C23C16/4405 , Y10S438/905 , Y10S438/906
摘要： A low temperature in-situ precleaning process for a semiconductor surface is disclosed. Ambient reactant gases, such as NF.sub.3 and GeH.sub.4, having a partial pressure of between approximately 10.sup.-8 and 700 Torr, are pulsed in a batch furnace at temperatures in the approximate range of 250 to 950 degrees Celsius and pressure in the approximate range of 4.times.10.sup.3 to 20.times.10.sup.3 Torr. This forms material on the surface that easily vaporizes in that temperature and pressure range, providing a clean surface for formation of the next layer. A similar in-situ cleaning process is performed at temperature ranges of between approximately 300 to 1,000 degrees Celsius for the equipment utilized in processing semiconductor substrates.
摘要翻译：公开了半导体表面的低温原位预清洗方法。具有介于约10-8和700托之间的分压的环境反应物气体，例如NF 3和GeH 4在分压炉中在大约250至950摄氏度的温度下脉冲，压力约为4×10 3 至20x103乇。这在表面上形成在该温度和压力范围内容易蒸发的材料，提供用于形成下一层的干净的表面。对于处理半导体衬底中使用的设备，在大约300至1000摄氏度之间的温度范围内进行类似的原位清洁过程。

73. 发明授权

US5989338A Method for depositing cell nitride with improved step coverage using MOCVD in a wafer deposition system 失效
标题翻译：在晶片沉积系统中使用MOCVD沉积具有改进的台阶覆盖的单元氮化物的方法
公开(公告)号：US5989338A
公开(公告)日：1999-11-23
申请号：US561735
申请日：1995-11-22
申请人： Scott J. DeBoer , Randhir P. S. Thakur
发明人： Scott J. DeBoer , Randhir P. S. Thakur
IPC分类号： C30B25/02 , H01L21/02 , H01L21/314 , H01L21/318 , C30B25/04
CPC分类号： H01L28/40 , C30B25/02 , C30B29/38 , H01L21/3185
摘要： An embodiment of the present invention teaches a method for forming a storage capacitor during semiconductor memory device fabrication, the method comprising the steps of: forming a first capacitor plate structure comprising a polysilicon material having an aspect ratio comprising a vertical component and a horizontal component; wherein the vertical component of the first capacitor plate structure is greater in dimension than the horizontal component of the first capacitor plate structure; depositing a silicon nitride layer over the first capacitor plate structure by exposing the first capacitor plate structure to a gas vapor phase of an organometallic precursor and to an nitrogen based gas in an Metal Organic Chemical Vapor Deposition (MOCVD) chamber; and forming a second capacitor plate structure over the silicon nitride layer, the second capacitor plate structure being positioned to span at least a portion of the first capacitor plate structure.
摘要翻译：本发明的实施例教导了一种在半导体存储器件制造期间形成存储电容器的方法，该方法包括以下步骤：形成第一电容器板结构，其包括具有垂直分量和水平分量的纵横比的多晶硅材料; 其中所述第一电容器板结构的垂直分量的尺寸大于所述第一电容器板结构的水平分量; 通过在金属有机化学气相沉积（MOCVD）室中将第一电容器板结构暴露于有机金属前体的气相和氮基气体，在第一电容器板结构上沉积氮化硅层; 以及在所述氮化硅层上形成第二电容器板结构，所述第二电容器板结构被定位成跨越所述第一电容器板结构的至少一部分。

74. 发明授权

US5953621A Method for forming a self-aligned isolation trench 失效
标题翻译：用于形成自对准隔离沟槽的方法
公开(公告)号：US5953621A
公开(公告)日：1999-09-14
申请号：US985588
申请日：1997-12-05
申请人： Fernando Gonzalez , David Chapek , Randhir P. S. Thakur
发明人： Fernando Gonzalez , David Chapek , Randhir P. S. Thakur
IPC分类号： H01L21/762
CPC分类号： H01L21/76237
摘要： The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross section of which has a nail shape in cross section.
摘要翻译：本发明涉及一种用于在半导体衬底中形成隔离沟槽结构的方法，而不会在其上表面造成有害的地形凹陷，这导致电流和电荷泄漏到相邻的有效区域。本发明的方法在半导体衬底上形成衬垫氧化物，然后在衬底氧化物上形成氮化物层。用掩模对氮化物层进行图案化并蚀刻以暴露焊盘氧化物层的一部分并保护半导体衬底中保留被氮化物层覆盖的有源区。第二电介质层基本上顺应地形成在焊盘氧化物层和第一电介质层的剩余部分上。然后进行间隔物蚀刻以从第二介电层形成间隔物。间隔物与第一电介质层的剩余部分接触。隔离沟蚀刻遵循间隔物蚀刻。可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。在第一介电层的剩余部分上基本上顺应地形成保形层，并基本上填充隔离沟槽。通过CMP或通过回蚀或其组合，可以平铺保形层。填充结构的隔离沟槽结果。所得到的结构具有法兰和轴，其横截面具有指甲形状。

75. 发明授权

US5837580A Method to form hemi-spherical grain (HSG) silicon 失效
公开(公告)号：US5837580A
公开(公告)日：1998-11-17
申请号：US842303
申请日：1997-04-23
申请人： Randhir P. S. Thakur , Lyle D. Breiner
发明人： Randhir P. S. Thakur , Lyle D. Breiner
IPC分类号： H01L21/02 , H01L21/205 , H01L21/3213 , H01L21/8242
CPC分类号： H01L28/84 , H01L21/02532 , H01L21/02576 , H01L21/02587 , H01L21/0262 , H01L21/32135 , H01L28/90 , Y10S438/964
摘要： An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C.; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.

76. 发明授权

US5825498A Ultraviolet light reflectance method for evaluating the surface characteristics of opaque materials 失效
标题翻译：用于评估不透明材料表面特性的紫外光反射率法
公开(公告)号：US5825498A
公开(公告)日：1998-10-20
申请号：US596469
申请日：1996-02-05
申请人： Randhir P. S. Thakur , Michael Nuttall , J. Brett Rolfson , Robert James Burke
发明人： Randhir P. S. Thakur , Michael Nuttall , J. Brett Rolfson , Robert James Burke
IPC分类号： G01B11/30 , G01B11/00
CPC分类号： G01B11/303
摘要： Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths used. This includes information pertaining to the roughness and surface area, as well as other surface characteristics such as grain size, grain density, grain shape, and boundary size between the grains. Surface characteristic evaluation can be conducted in-process in a manner which is non-destructive to the test sample. The method is particularly useful for determining the capacitance of highly granular polysilicon test samples used in the construction of capacitator plates in integrated circuit technology.
摘要翻译：公开了一种用于分析不透明材料的表面特性的方法。该方法在一个实施方案中包括使用UV反射计来构建来自一组对照样品的数据的校准矩阵，并将期望的表面特性如粗糙度或表面积与对照样品的一组反射率相关联。然后使用UV反射计测量未知表面特性的测试样品的反射率。反射率以各种波长进行，优选在约250纳米至约400纳米之间。然后将这些反射率与校准矩阵的反射率进行比较，以便将校准矩阵中最接近的数据相关联。通过这样做，由于所使用的波长范围广，因此得出各种信息。这包括关于粗糙度和表面积的信息，以及晶粒之间的其他表面特性，例如晶粒尺寸，晶粒密度，晶粒形状和边界尺寸。表面特性评估可以以对测试样品非破坏性的方式进行。该方法对于确定集成电路技术中用于构造电容器板的高度粒状多晶硅测试样品的电容特别有用。

77. 发明授权

US5783804A Reflectance method for accurate process calibration in semiconductor substrate heat treatment 失效
标题翻译：半导体衬底热处理精确过程校准的反射方法
公开(公告)号：US5783804A
公开(公告)日：1998-07-21
申请号：US813368
申请日：1997-03-07
申请人： Robert James Burke , Russell C. Zahorik , Paul A. Paduano , Randhir P. S. Thakur
发明人： Robert James Burke , Russell C. Zahorik , Paul A. Paduano , Randhir P. S. Thakur
IPC分类号： G01K11/14 , G03F7/20 , G05D23/26 , G05D23/27 , H01L21/66 , H05B1/02
CPC分类号： G05D23/27 , G01K11/14 , G03F7/70616 , G05D23/1919 , G05D23/26 , H01L22/12
摘要： A nondestructive product level calibration method which is based on reflectance of intensity of UV and visible light that is measured from the top surface of a semiconductor wafer in a RTP closed loop process control environment in which the temperature of the wafer is regulated as a function of reflectivity of radiation at a preselected wavelength from the top surface of the wafer. In the method, sheet resistance of the wafer is measured as a function of the intensity of the UV and IR light directed at the wafer over a predetermined temperature and time range. Then, the reflectance intensity off wafer is measured to develop a model of the top surface. The reflectance model will indicate a wavelength where the reflectance is the greatest. Next, the wafer is subjected to UV radiation at the most sensitive wavelength and the reflectance is plotted against intensity of heat treatment. Then, notice is taken that the reflectance detected directly corresponds to a ratio of temperature over time measured in the first step. Thus, the reflectance at a particular wavelength of UV light corresponds to a specific and discrete temperature so that the degree of heat treatment to which the wafer has been exposed is known.
摘要翻译：一种非破坏性的产品水平校准方法，其基于在封闭环路过程控制环境中从半导体晶片的顶表面测量的UV和可见光强度的反射率，其中晶片的温度被调节为来自晶片顶表面的预选波长的辐射的反射率。在该方法中，测量晶片的薄层电阻作为在预定温度和时间范围内指向晶片的UV和IR光的强度的函数。然后，测量离开晶片的反射率强度，以形成顶表面的模型。反射率模型将表示反射率最大的波长。接下来，晶片经受最敏感波长的紫外线辐射，反射率相对于热处理强度作图。然后，注意到直接检测到的反射率对应于在第一步中测量的随时间的温度比。因此，UV光的特定波长处的反射率对应于特定和离散的温度，使得已经暴露了晶片的热处理程度是已知的。

78. 发明授权

US5780364A Method to cure mobile ion contamination in semiconductor processing 失效
公开(公告)号：US5780364A
公开(公告)日：1998-07-14
申请号：US759152
申请日：1996-11-27
申请人： Randhir P. S. Thakur
发明人： Randhir P. S. Thakur
IPC分类号： H01L21/322 , H01L23/31 , H01L21/31
CPC分类号： H01L23/3171 , H01L21/3221 , H01L2924/0002 , H01L2924/19041 , Y10S148/112
摘要： A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.

79. 发明授权

US5712186A Method for growing field oxide to minimize birds' beak length 失效
标题翻译：生长场氧化物以最小化鸟的喙长度的方法
公开(公告)号：US5712186A
公开(公告)日：1998-01-27
申请号：US662852
申请日：1996-06-12
申请人： Randhir P. S. Thakur , Michael Nuttall , Pai-Hung Pan
发明人： Randhir P. S. Thakur , Michael Nuttall , Pai-Hung Pan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76213
摘要： A method for forming field oxide isolation regions using oxygen implantation is described. An oxidation resistant layer such as silicon nitride is formed on a silicon substrate, and acts as an oxidation mask. An opening is then formed in the nitride layer, where field oxide is desired. In one embodiment of the invention, oxygen is implanted into this opening, followed by thermal oxidation. In a second embodiment of the invention, the opening is thermally oxidized, followed by a deep oxygen implant and anneal. Encroachment of the field oxide under the nitride layer is decreased, resulting in a minimum "birds' beak" length.
摘要翻译：描述了使用氧注入形成场氧化物隔离区的方法。在硅衬底上形成氮化硅等抗氧化层，作为氧化掩模。然后在氮化物层中形成开口，其中期望场氧化物。在本发明的一个实施方案中，将氧气注入该开口，随后进行热氧化。在本发明的第二实施例中，开口被热氧化，随后进行深氧注入和退火。在氮化物层下的场氧化物的侵蚀减少，导致最小的“鸟”喙长度。

80. 发明授权

US5691228A Semiconductor processing method of making a hemispherical grain (HSG) polysilicon layer 失效
标题翻译：制造半球形晶粒（HSG）多晶硅层的半导体加工方法
公开(公告)号：US5691228A
公开(公告)日：1997-11-25
申请号：US591227
申请日：1996-01-18
申请人： Er-Xang Ping , Randhir P. S. Thakur
发明人： Er-Xang Ping , Randhir P. S. Thakur
IPC分类号： H01L21/02 , H01L21/70 , H01L27/00
CPC分类号： H01L28/84
摘要： A semiconductor processing method of providing a hemispherical grain polysilicon layer atop a substrate includes, a) providing a substantially amorphous layer of silicon over a substrate at a selected temperature; b) raising the temperature of the substantially amorphous silicon layer to a higher dielectric layer deposition temperature, the temperature raising being effective to transform the amorphous silicon layer into hemispherical grain polysilicon; and c) depositing a dielectric layer over the silicon layer at the higher dielectric deposition temperature. Transformation to hemispherical grain might occur during the temperature rise to the higher dielectric layer deposition temperature, after the higher dielectric layer deposition temperature has been achieved but before dielectric layer deposition, or after the higher dielectric layer deposition temperature has been achieved and during dielectric layer deposition. The temperature raising step can include initially raising the silicon layer temperature to an annealing temperature below the higher dielectric layer deposition temperature, and maintaining the silicon layer at the annealing temperature for a time period effective to increase its degree of surface roughness. Subsequently the silicon layer temperature is raised to the higher dielectric layer deposition temperature, with such further increasing the degree of surface roughness of the resultant silicon layer.
摘要翻译：在衬底顶上提供半球形晶粒多晶硅层的半导体处理方法包括：a）在所选择的温度下在衬底上提供基本非晶硅层; b）将基本非晶硅层的温度提高到更高的介电层沉积温度，升温可有效地将非晶硅层转变成半球形晶粒多晶硅; 和c）在更高的介电沉积温度下在硅层上沉积介电层。在高电介质层沉积温度达到较高的介电层沉积之后，或者在实现更高的介电层沉积温度之后，以及在介电层沉积期间，在温度升高到更高的介电层沉积温度的过程中，可能会发生半球形晶粒的转变。升温步骤可以包括首先将硅层温度升高到低于较高电介质层沉积温度的退火温度，并且将硅层保持在退火温度一段有效增加其表面粗糙度的时间段。随后，硅层温度升至更高的介电层沉积温度，这样进一步增加所得硅层的表面粗糙度。

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