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71. 发明授权

US07006403B2 Self timed bit and read/write pulse stretchers 有权
标题翻译：自定时位和读/写脉冲担架
公开(公告)号：US07006403B2
公开(公告)日：2006-02-28
申请号：US10736415
申请日：2003-12-15
申请人： Rajiv V. Joshi , Arthur D. Tuminaro
发明人： Rajiv V. Joshi , Arthur D. Tuminaro
IPC分类号： G11C7/22 , G11C8/10 , G11C8/18 , G11C11/413
CPC分类号： G11C7/222 , G11C7/22 , G11C11/419 , G11C2207/2281 , G11C2207/229
摘要： Bit and write decode/drivers, a random access memory (RAM) including the decode/drivers and an IC with a static RAM (SRAM) including the decode/drivers. The decode/drivers are clocked by a local clock and each produce access pulses wider than corresponding clock pulses. The bit decode/driver produces bit select pulses that are wider than a word select pulse and the write decode/driver produces write pulses that are wider than the bit select pulses for stable self timed RAM write accesses.
摘要翻译：位和写入解码/驱动器，包括解码/驱动器的随机存取存储器（RAM）和具有包括解码/驱动器的静态RAM（SRAM）的IC。解码/驱动器由本地时钟计时，并产生比对应的时钟脉冲宽的访问脉冲。位解码/驱动器产生比字选择脉冲宽的位选择脉冲，写解码/驱动器产生比用于稳定自定时RAM写访问的位选择脉冲宽的写入脉冲。

72. 发明授权

US06964908B2 Metal-insulator-metal capacitor and method of fabricating same 失效
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US06964908B2
公开(公告)日：2005-11-15
申请号：US10643307
申请日：2003-08-19
申请人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
发明人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L21/28 , H01L21/308
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

73. 发明授权

US06934182B2 Method to improve cache capacity of SOI and bulk 有权
标题翻译：提高SOI和散货的高速缓存容量的方法
公开(公告)号：US06934182B2
公开(公告)日：2005-08-23
申请号：US10678508
申请日：2003-10-03
申请人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
发明人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
IPC分类号： G11C11/41 , G11C11/00 , G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412
摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.
摘要翻译：提供了设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有比下拉电阻高的阈值电压晶体管，这使得SRAM单元能够在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不影响单元在访问期间的稳定性。并且，通过减小单元尺寸，芯片的整体设计布局也可能降低。

74. 发明授权

US06920061B2 Loadless NMOS four transistor dynamic dual Vt SRAM cell 有权
公开(公告)号：US06920061B2
公开(公告)日：2005-07-19
申请号：US10649200
申请日：2003-08-27
申请人： Azeez Bhavnagarwala , Rajiv V. Joshi , Stephen V. Kosonocky
发明人： Azeez Bhavnagarwala , Rajiv V. Joshi , Stephen V. Kosonocky
IPC分类号： G11C11/418 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.

75. 发明授权

US06868000B2 Coupled body contacts for SOI differential circuits 有权
标题翻译：用于SOI差分电路的耦合体触点
公开(公告)号：US06868000B2
公开(公告)日：2005-03-15
申请号：US10436432
申请日：2003-05-12
申请人： Yuen H. Chan , Rajiv V. Joshi , Antonio R. Pelella
发明人： Yuen H. Chan , Rajiv V. Joshi , Antonio R. Pelella
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.
摘要翻译：绝缘体上硅（SOI）CMOS电路，宏和集成电路（IC）芯片。芯片或宏可以包括部分耗尽（PD）SOI CMOS中的SRAM。大多数场效应晶体管（FET）不具有主体接触。否则表现出对历史影响敏感的场效应物体接触。每个这样的FET的身体接触件连接到至少一个其他身体接触。可以向所选择的FET提供背偏置电压。

76. 发明授权

US06788566B1 Self-timed read and write assist and restore circuit 失效
标题翻译：自定义读写辅助和恢复电路
公开(公告)号：US06788566B1
公开(公告)日：2004-09-07
申请号：US10694698
申请日：2003-10-28
申请人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
发明人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
IPC分类号： G11C1100
CPC分类号： G11C11/413 , G11C7/12
摘要： A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.
摘要翻译：用于存储器件的读和写辅助和恢复电路包括第一器件，其响应于位线上的电位，使得位线上的电位激活第一器件。第二设备由第一设备驱动，使得当第一设备被激活时，位线电位的变化通过第二设备在字线活动时段期间的正反馈得到加强，从而能够使数据丢失的回写成为可能的耦合到位线的存储单元晶体管中的阈值电压波动。

77. 发明授权

US06714476B2 Memory array with dual wordline operation 有权
标题翻译：具有双字操作的内存阵列
公开(公告)号：US06714476B2
公开(公告)日：2004-03-30
申请号：US09783918
申请日：2001-02-15
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/10 , G11C11/404 , G11C11/405 , G11C11/4087
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括字线解码电路，用于在单电池和双电池阵列操作之间交换DRAM阵列。字线解码电路包括用于接收控制信号并将逻辑输出输出到字线激活电路的预解码器电路。字线激活电路然后激活穿过阵列的至少一个字线，用于在单电池阵列操作和双电池阵列操作之间互换DRAM阵列内的存储器单元。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

78. 发明授权

US06549450B1 Method and system for improving the performance on SOI memory arrays in an SRAM architecture system 有权
标题翻译：用于提高SRAM架构系统中SOI存储器阵列性能的方法和系统
公开(公告)号：US06549450B1
公开(公告)日：2003-04-15
申请号：US09708142
申请日：2000-11-08
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.
摘要翻译：本发明提供一种SOI SRAM架构系统，其在阵列空闲或睡眠模式期间将所有位线保持在较低电压电平，例如接地或Vdd的一部分。优选地，位线被保持在大约等于Vdd-Vth的电压电平，其中Vth表示SRAM单元的传送器件的阈值电压。这防止了阵列的每个电池的转移装置的主体区域完全充电，因此系统避免了由部分耗尽的SOI衬底上制造的器件引起的寄生双极泄漏电流效应。而且，在空闲或睡眠模式期间，如果所有位线都保持在Vdd-Vth电压电平左右，则SRAM架构系统的功耗将会降低。这是因为通过所有SRAM单元的传输门之一的泄漏路径被极大地最小化。在本发明的SOI SRAM架构系统中，在空闲或休眠模式之前首先访问SOI SRAM阵列之前，位线被快速地提升到Vdd。因此，传送装置的SOI体区域不会充足的时间。在阵列访问之后，如果阵列空闲一段时间，则位线再次放电到较低的电压电平。为了实现这一点，本发明的SOI SRAM架构系统包括用于接收指示阵列的操作模式的至少一个信号并且相应地对阵列位线进行充电和放电的电路。

79. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

80. 发明授权

US06445626B1 Column redundancy architecture system for an embedded DRAM 失效
标题翻译：用于嵌入式DRAM的列冗余架构系统
公开(公告)号：US06445626B1
公开(公告)日：2002-09-03
申请号：US09821443
申请日：2001-03-29
申请人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
发明人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/846 , G11C2207/104
摘要： A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
摘要翻译：公开了一种具有宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的列冗余架构系统，其为eDRAM的缺陷数据库提供列冗余。在eDRAM阵列测试期间，每个微单元块的内部生成的列地址存储在存储器件中。公开了两种冗余重路由机制。第一个冗余重路由机制选择eDRAM的至少一个有缺陷的数据库，并用至少一个冗余数据线直接替换有缺陷的数据库。第二个冗余重路由机制丢弃有缺陷的数据列，并用相邻的数据列替换它。随后，数据线列中的数据栏将被替换为包含冗余数据列的下一个相邻的数据列。

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