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1. 发明授权

US6151200A Method of discharging SOI floating body charge 失效
标题翻译：放电SOI浮体电荷的方法
公开(公告)号：US6151200A
公开(公告)日：2000-11-21
申请号：US452934
申请日：1999-12-02
申请人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
发明人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
IPC分类号： H02H9/04 , H02H9/00
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译：通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。

2. 发明授权

US5229322A Method of making low resistance substrate or buried layer contact 失效
标题翻译：制造低电阻衬底或掩埋层接触的方法
公开(公告)号：US5229322A
公开(公告)日：1993-07-20
申请号：US804228
申请日：1991-12-05
申请人： Shao-Fu S. Chu , Kyong-Min Kim , Shaw-Ning Mei , Mary J. Saccamango , Donald R. Vigliotti , Robert J. von Gutfeld
发明人： Shao-Fu S. Chu , Kyong-Min Kim , Shaw-Ning Mei , Mary J. Saccamango , Donald R. Vigliotti , Robert J. von Gutfeld
IPC分类号： H01L21/28 , H01L21/74 , H01L29/41
CPC分类号： H01L21/743 , Y10S117/904 , Y10S148/09
摘要： An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.
摘要翻译：用于形成与半导体结构的衬底或掩埋层的连接的便宜且可靠的技术使用激光来熔化轻掺杂层和高度掺杂的下层的小的选定区域。当熔体被允许重结晶时，杂质的极快速扩散和材料在熔体液相内的混合会快速产生均匀掺杂的导电区域。

3. 发明授权

US06549450B1 Method and system for improving the performance on SOI memory arrays in an SRAM architecture system 有权
标题翻译：用于提高SRAM架构系统中SOI存储器阵列性能的方法和系统
公开(公告)号：US06549450B1
公开(公告)日：2003-04-15
申请号：US09708142
申请日：2000-11-08
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.
摘要翻译：本发明提供一种SOI SRAM架构系统，其在阵列空闲或睡眠模式期间将所有位线保持在较低电压电平，例如接地或Vdd的一部分。优选地，位线被保持在大约等于Vdd-Vth的电压电平，其中Vth表示SRAM单元的传送器件的阈值电压。这防止了阵列的每个电池的转移装置的主体区域完全充电，因此系统避免了由部分耗尽的SOI衬底上制造的器件引起的寄生双极泄漏电流效应。而且，在空闲或睡眠模式期间，如果所有位线都保持在Vdd-Vth电压电平左右，则SRAM架构系统的功耗将会降低。这是因为通过所有SRAM单元的传输门之一的泄漏路径被极大地最小化。在本发明的SOI SRAM架构系统中，在空闲或休眠模式之前首先访问SOI SRAM阵列之前，位线被快速地提升到Vdd。因此，传送装置的SOI体区域不会充足的时间。在阵列访问之后，如果阵列空闲一段时间，则位线再次放电到较低的电压电平。为了实现这一点，本发明的SOI SRAM架构系统包括用于接收指示阵列的操作模式的至少一个信号并且相应地对阵列位线进行充电和放电的电路。

4. 发明授权

US5504362A Electrostatic discharge protection device 失效
标题翻译：静电放电保护装置
公开(公告)号：US5504362A
公开(公告)日：1996-04-02
申请号：US306532
申请日：1994-09-14
申请人： Mario M. Pelella , Ralph W. Young , Giovanni Fiorenza , Mary J. Saccamango
发明人： Mario M. Pelella , Ralph W. Young , Giovanni Fiorenza , Mary J. Saccamango
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： A thick-oxide ESD transistor for a BiCMOS integrated circuit has its source/drain contacts formed of the BiCMOS base or emitter polysilicon and its source/drain formed by an outdiffusion of the respective polysilicon contact. In one embodiment the BiCMOS resistor doping deepens the ESD source/drains, and in another embodiment the BiCMOS collector reach through doping deepens the ESD source/drains. The entire ESD transistor is fabricated from a standard BiCMOS process without any additional steps, has an area of about 100 square microns, can shunt up to 6000 volts, and has a turn-on time of about 10 picoseconds.
摘要翻译：用于BiCMOS集成电路的厚氧化物ESD晶体管具有由BiCMOS基极或发射极多晶硅形成的源极/漏极接触，并且其源极/漏极由相应的多晶硅接触的扩散扩散形成。在一个实施例中，BiCMOS电阻器掺杂加深ESD源极/漏极，并且在另一个实施例中，BiCMOS集电极通过掺杂物达到深化ESD源极/漏极。整个ESD晶体管由标准的BiCMOS工艺制造而无需任何附加步骤，面积约为100平方微米，可分流至6000伏，并具有约10皮秒的导通时间。

5. 发明授权

US5266505A Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors 失效
标题翻译：在平面外延基极双极晶体管中自对准植入物的图像反转过程
公开(公告)号：US5266505A
公开(公告)日：1993-11-30
申请号：US994743
申请日：1992-12-22
申请人： David C. Ahlgren , Shao-Fu S. Chu , Mary J. Saccamango , David A. Sunderland , Tze-Chiang Chen
发明人： David C. Ahlgren , Shao-Fu S. Chu , Mary J. Saccamango , David A. Sunderland , Tze-Chiang Chen
IPC分类号： H01L21/331 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66287 , Y10S148/072
摘要： An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.
摘要翻译：用于自对准植入物的图像反转过程，其中开口中的掩模开口和插塞用于使掩模开口中的一个植入物，围绕开口的区域中的另一个自对准植入物，以及自对准电极形成在开口。

6. 发明授权

US6078058A SOI floating body charge monitor circuit and method 失效
标题翻译： SOI浮体电荷监测电路及方法
公开(公告)号：US6078058A
公开(公告)日：2000-06-20
申请号：US35407
申请日：1998-03-05
申请人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
发明人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
IPC分类号： H02H9/04 , H01L23/58 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译：通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。

7. 发明授权

US5736891A Discharge circuit in a semiconductor memory 失效
标题翻译：半导体存储器中的放电电路
公开(公告)号：US5736891A
公开(公告)日：1998-04-07
申请号：US585336
申请日：1996-01-11
申请人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango , Hyun Jong Shin
发明人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango , Hyun Jong Shin
IPC分类号： G11C16/30 , H03K17/10 , H03K17/687
CPC分类号： H03K17/102 , G11C16/30 , H03K17/6872
摘要： A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.
摘要翻译：用于半导体存储器的放电电路包括第一节点，用于接收具有第一和第二状态的控制信号的第二节点和连接在第一节点和地电位之间的电路以及连接到第二节点的电路。当控制信号具有第一状态时，电路将第一节点耦合到地电位，并且当控制信号具有第二状态时，电路基本上将第一节点与地电势隔离。电路包括用于限定第一节点和地电位之间的电流路径的第一子电路。第一分支电路包括串联连接的多个晶体管，每个晶体管具有栅极，源极和漏极。当控制信号具有第二状态时，电路还包括用于实现第一子电路的晶体管的预定栅极至源极和漏极至源极电压的第二子电路。

8. 发明授权

US5573964A Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer 失效
标题翻译：利用来自掺杂剂源层的扩散制造具有自对准底栅的薄膜晶体管的方法
公开(公告)号：US5573964A
公开(公告)日：1996-11-12
申请号：US559809
申请日：1995-11-17
申请人： Louis L. Hsu , Mary J. Saccamango , Joseph F. Shepard
发明人： Louis L. Hsu , Mary J. Saccamango , Joseph F. Shepard
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66765 , H01L29/42384 , H01L29/78621 , H01L29/4908
摘要： A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.
摘要翻译：公开了一种在具有绝缘表面层的衬底上制造薄膜晶体管（TFT）的简单方法。掺杂剂源层的一层沉积在绝缘层上，随后使用掺杂剂源层作为蚀刻停止层，由栅极多晶硅，栅极绝缘体和保护性多晶硅构成的栅极叠层。侧壁间隔件形成为与栅极堆叠接触。沉积并图案化TFT体多晶硅，从而以自对准的方式形成源区和漏区。通过加热，来自掺杂剂源层的掺杂剂被驱动到源极/漏极和体内多晶硅层的偏移区域的一部分，同时也掺杂栅极多晶硅。

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