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1. 发明授权

US06920061B2 Loadless NMOS four transistor dynamic dual Vt SRAM cell 有权
公开(公告)号：US06920061B2
公开(公告)日：2005-07-19
申请号：US10649200
申请日：2003-08-27
申请人： Azeez Bhavnagarwala , Rajiv V. Joshi , Stephen V. Kosonocky
发明人： Azeez Bhavnagarwala , Rajiv V. Joshi , Stephen V. Kosonocky
IPC分类号： G11C11/418 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.

2. 发明授权

US07180818B2 High performance register file with bootstrapped storage supply and method of reading data therefrom 有权
标题翻译：具有引导存储供应的高性能寄存器文件和从其读取数据的方法
公开(公告)号：US07180818B2
公开(公告)日：2007-02-20
申请号：US10996311
申请日：2004-11-22
申请人： Rajiv V. Joshi , Azeez Bhavnagarwala
发明人： Rajiv V. Joshi , Azeez Bhavnagarwala
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C8/16
摘要： A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.
摘要翻译：多端口寄存器文件，包括一个或多个多端口寄存器文件的集成电路（IC）芯片以及从多端口寄存器文件读取数据的方法。在多端口寄存器文件中的存储锁存器的供应在访问期间选择性地被引导到电源电压之上。

3. 发明授权

US06788566B1 Self-timed read and write assist and restore circuit 失效
标题翻译：自定义读写辅助和恢复电路
公开(公告)号：US06788566B1
公开(公告)日：2004-09-07
申请号：US10694698
申请日：2003-10-28
申请人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
发明人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
IPC分类号： G11C1100
CPC分类号： G11C11/413 , G11C7/12
摘要： A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.
摘要翻译：用于存储器件的读和写辅助和恢复电路包括第一器件，其响应于位线上的电位，使得位线上的电位激活第一器件。第二设备由第一设备驱动，使得当第一设备被激活时，位线电位的变化通过第二设备在字线活动时段期间的正反馈得到加强，从而能够使数据丢失的回写成为可能的耦合到位线的存储单元晶体管中的阈值电压波动。

4. 发明授权

US07898894B2 Static random access memory (SRAM) cells 有权
标题翻译：静态随机存取存储器（SRAM）单元
公开(公告)号：US07898894B2
公开(公告)日：2011-03-01
申请号：US11402401
申请日：2006-04-12
申请人： Leland Chang , Rajiv V. Joshi , Stephen V. Kosonocky
发明人： Leland Chang , Rajiv V. Joshi , Stephen V. Kosonocky
IPC分类号： G11C11/41 , G11C8/16 , G11C5/06
CPC分类号： G11C11/412
摘要： The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.
摘要翻译：本发明提供一种改进的SRAM单元。具体地说，本发明提供一种具有一组或多组堆叠晶体管的SRAM单元，用于在读取操作期间隔离单元。根据实施例，本发明的SRAM单元可以具有八个或十个晶体管。无论如何，本发明的SRAM单元通常包括分离/去耦合的写字和读字线，一对交叉耦合的反相器和耦合到写字线的互补的一对通过晶体管。在SRAM单元内实现的每组堆叠晶体管具有耦合到位线以及读取字线的晶体管。

5. 发明授权

US06791886B1 SRAM cell with bootstrapped power line 有权
标题翻译：具有自举电源线的SRAM单元
公开(公告)号：US06791886B1
公开(公告)日：2004-09-14
申请号：US10448723
申请日：2003-05-30
申请人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
发明人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Rajiv V. Joshi
IPC分类号： G11C1604
CPC分类号： G11C11/413 , G11C5/14 , G11C8/08
摘要： A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.
摘要翻译：存储单元包括用于选择性地将电源电压节点连接到电力线的至少一个有源装置。电源线将电容元件通过至少一个有源器件耦合到电源电压节点，以在访问存储节点时保持高状态。高状态由通过添加电容元件而产生的升压来提供。

6. 发明授权

US08767501B2 Self-reconfigurable address decoder for associative index extended caches 有权
标题翻译：用于关联索引扩展缓存的自重配置地址解码器
公开(公告)号：US08767501B2
公开(公告)日：2014-07-01
申请号：US13550762
申请日：2012-07-17
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G11C8/10
CPC分类号： G06F12/0864 , G06F2212/1021 , G11C15/04
摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
摘要翻译：关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作错过率。地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

7. 发明授权

US08578316B1 Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation 有权
公开(公告)号：US08578316B1
公开(公告)日：2013-11-05
申请号：US13607678
申请日：2012-09-08
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5018
摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

8. 发明申请

US20130289965A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

9. 发明申请

US20130289948A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
标题翻译：基于快速TCAD变换建模的场效应晶体管
公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

10. 发明申请

US20130042217A1 STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT 失效
标题翻译：集成电路布局的结构迁移
公开(公告)号：US20130042217A1
公开(公告)日：2013-02-14
申请号：US13205186
申请日：2011-08-08
申请人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
发明人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.
摘要翻译：迁移电路布局的方法和系统。使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在平面图布局上使用基于形状约束的缩放。细胞被放置在由平面图布局定义的位置处。使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

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