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71. 发明申请

US20070181930A1 Structure and method of making double-gated self-aligned finfet having gates of different lengths 有权
标题翻译：制作具有不同长度的门的双门控自对准finfet的结构和方法
公开(公告)号：US20070181930A1
公开(公告)日：2007-08-09
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
发明人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

72. 发明申请

US20060091450A1 Dual function FinFET, finmemory and method of manufacture 有权
公开(公告)号：US20060091450A1
公开(公告)日：2006-05-04
申请号：US10978951
申请日：2004-11-01
申请人： Huilong Zhu , Bruce Doris , Jochen Beintner
发明人： Huilong Zhu , Bruce Doris , Jochen Beintner
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L29/78684 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/4908 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

73. 发明授权

US07037794B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 失效
标题翻译：提高了用于多栅极氧化和侧壁保护的STI工艺，在应变Si / SGOI结构上具有升高的源极/漏极
公开(公告)号：US07037794B2
公开(公告)日：2006-05-02
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

74. 发明申请

US20060068596A1 Formation of Controlled Sublithographic Structures 失效
标题翻译：控制亚光刻结构的形成
公开(公告)号：US20060068596A1
公开(公告)日：2006-03-30
申请号：US10711683
申请日：2004-09-30
申请人： David Dobuzinsky , Jochen Beintner , Siddhartha Panda
发明人： David Dobuzinsky , Jochen Beintner , Siddhartha Panda
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3088 , H01L21/32139 , H01L29/66795 , H01L29/785
摘要： A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.
摘要翻译：用于形成诸如翅片之类的亚光刻结构的工艺使用硬掩模上方的硬掩模保护层来在干蚀刻步骤期间吸收损伤，从而保持硬掩模中的对称性并消除缺陷源。

75. 发明申请

US20060030106A1 Gate conductor isolation and method for manufacturing same 有权
公开(公告)号：US20060030106A1
公开(公告)日：2006-02-09
申请号：US10912005
申请日：2004-08-05
申请人： Jochen Beintner
发明人： Jochen Beintner
IPC分类号： H01L21/336
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10894
摘要： A method for processing a semiconductor device includes providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate. The method includes stripping the pad nitride, depositing an array top oxide layer over the pad oxide formed on the semiconductor substrate in the array area and the support area, and planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area. The method further includes forming a wordline stack comprising a nitride layer, a gate conductor and an insulator, and etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.

76. 发明授权

US06933206B2 Trench isolation employing a high aspect ratio trench 失效
标题翻译：使用高纵横比沟槽的沟槽隔离
公开(公告)号：US06933206B2
公开(公告)日：2005-08-23
申请号：US10683668
申请日：2003-10-10
申请人： Jochen Beintner , Andreas Knorr
发明人： Jochen Beintner , Andreas Knorr
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.
摘要翻译：隔离沟槽，形成在半导体衬底中，并且填充有至少一个绝缘衬层，绝缘衬垫层沿隔离沟槽的侧壁和底部区域沉积，并且至少一层硅衬层沉积在绝缘衬层的顶部。去除绝缘衬垫层的上部，并去除硅衬层。沟槽的剩余部分填充有另一绝缘层。

77. 发明申请

US20050124099A1 SELFALIGNED SOURCE/DRAIN FINFET PROCESS FLOW 有权
标题翻译：自熔源/漏液FINFET工艺流程
公开(公告)号：US20050124099A1
公开(公告)日：2005-06-09
申请号：US10731584
申请日：2003-12-09
申请人： Jochen Beintner , Edward Nowak
发明人： Jochen Beintner , Edward Nowak
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/786 , H01L21/00
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A selfaligned FinFET is fabricated by defining a set of fins in a semiconductor wafer, depositing gate material over the fins, defining a gate hardmask having a thickness sufficient to withstand later etching steps, etching the gate material outside the hardmask to form the gate, depositing a conformal layer of insulator over the gate and the fins, etching the insulator anistotropically until the insulator over the fins is removed down to the substrate, the hardmask having a thickness such that a portion of the hardmask remains over the gate and sidewalls remain on the gate, and forming source and drain areas in the exposed fins while the gate is protected by the hardmask material.
摘要翻译：通过在半导体晶片中限定一组翅片来制造自对准的FinFET，在栅极上沉积栅极材料，限定具有足以承受后续蚀刻步骤的厚度的栅极硬掩模，蚀刻硬掩模外部的栅极材料以形成栅极，沉积在栅极和散热片上形成绝缘体的保形层，蚀刻绝缘子向各向异性，直到鳍片上的绝缘体向下移动到衬底，硬掩模具有使得硬掩模的一部分保留在栅极和侧壁上的厚度门，并且在暴露的翅片中形成源极和漏极区域，同时门被硬掩模材料保护。

78. 发明申请

US20050121412A1 Pull-back method of forming fins in FinFETs 失效
标题翻译： FinFET形成翅片的回拉法
公开(公告)号：US20050121412A1
公开(公告)日：2005-06-09
申请号：US10730234
申请日：2003-12-09
申请人： Jochen Beintner , Dureseti Chidambarrao , Yujun Li , Kenneth Settlemyer
发明人： Jochen Beintner , Dureseti Chidambarrao , Yujun Li , Kenneth Settlemyer
IPC分类号： H01L21/308 , H01L21/336 , H01L29/78 , H01L29/786 , B44C1/22 , C25F3/00
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L29/66795
摘要： A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.
摘要翻译：一种形成具有FinFET晶体管的集成电路的方法包括形成次光刻鳍片的方法，其中限定包含一对鳍片的硅块的掩模，所述掩模的宽度被减小或者被拉回每边的一个鳍片的厚度，之后在第一掩模周围形成第二掩模，使得在去除第一掩模之后，在第二掩模中保留具有一对散热片之间的间隔距离的宽度的孔。当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过拉回步骤限定翅片厚度。一种替代方法是使用相反极性的光刻法，首先在两个散热片之间光刻地限定中心蚀刻孔径，然后通过拉回步骤扩大孔径的宽度，以便用耐蚀刻塞子填充加宽的孔径限定了一对翅片，从而设置翅片宽度而没有对准kstep。

79. 发明授权

US06893911B2 Process integration for integrated circuits 失效
标题翻译：集成电路的过程集成
公开(公告)号：US06893911B2
公开(公告)日：2005-05-17
申请号：US10249100
申请日：2003-03-16
申请人： Jochen Beintner
发明人： Jochen Beintner
IPC分类号： H01L21/311 , H01L21/76 , H01L21/8238 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/945 , H01L27/10864 , H01L27/10894
摘要： A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a substrate prepared with a support region having an active area between first and second trench isolations. The top surfaces of the trench isolations extend above the surface of the substrate. First and second etch stop layers are deposited on the substrate, lining the substrate surface and trench isolations without filling the gap. The etch stop layers can be etched selective to each other and layers beneath and or above. The second etch stop layer includes horizontal and vertical portions. An etch selectively removes the vertical portions of the etch stop layer. An isotropic etch is then performed, removing exposed portions of the first etch stop layer. The second etch stop layer acts as an etch mask. The etch also creates an undercut beneath the second etch stop layer, exposing edge portions of the active area. The second etch stop layer is removed, following by oxidizing the edge portions of the active area unprotected by the first etch stop layer.
摘要翻译：公开了一种用于制造集成电路的工艺。特别地，该过程包括使活动区域的四舍五入。在一个实施方案中，制备具有在第一和第二沟槽隔离之间具有有效面积的支撑区的衬底。沟槽隔离物的顶表面在衬底的表面上方延伸。第一和第二蚀刻停止层沉积在衬底上，衬底衬底表面和沟槽隔离而不填充间隙。蚀刻停止层可以彼此选择性蚀刻，并在其下方或上方蚀刻。第二蚀刻停止层包括水平和垂直部分。蚀刻选择性地去除蚀刻停止层的垂直部分。然后执行各向同性蚀刻，去除第一蚀刻停止层的暴露部分。第二蚀刻停止层用作蚀刻掩模。蚀刻还在第二蚀刻停止层下方产生底切，暴露有源区域的边缘部分。除去第二蚀刻停止层，然后氧化未被第一蚀刻停止层保护的有源区的边缘部分。

80. 发明申请

US20050079730A1 Trench isolation employing a high aspect ratio trench 失效
公开(公告)号：US20050079730A1
公开(公告)日：2005-04-14
申请号：US10683668
申请日：2003-10-10
申请人： Jochen Beintner , Andreas Knorr
发明人： Jochen Beintner , Andreas Knorr
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.

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