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    • 71. 发明授权
    • Microelectromechanical system based sensors, sensor arrays, sensing systems, sensing methods and methods of fabrication
    • 基于微机电系统的传感器,传感器阵列,感测系统,感测方法和制造方法
    • US06844214B1
    • 2005-01-18
    • US10604850
    • 2003-08-21
    • Ping MeiDecai SunRobert A. Street
    • Ping MeiDecai SunRobert A. Street
    • B81B3/00H01L21/00H01L23/48H01R11/22
    • B81B3/0021B81B2201/0292B81B2201/038B81B2201/047B81B2203/0118B81C2201/0167H01R12/52
    • A microelectromechanical system (MEMS) based sensor comprises: a substrate defining a plane; a first conductive material layer having a first stress, a first portion of the first conductive material layer being connected to the substrate and extending in a substantially parallel direction to the plane defined by the substrate and a second portion being disconnected from the substrate and extending in a substantially non-parallel direction to the plane defined by the substrate; and a sensor material layer formed over at least the second portion of the first conductive material layer, the sensor material layer having a second stress that is less than the first stress of the first conductive material layer. The stresses form a stress gradient that bends the second portion of the first conductive material layer and the sensor material layer formed over the second portion of the first conductive material layer away from the substrate.
    • 基于微机电系统(MEMS)的传感器包括:限定平面的基板; 具有第一应力的第一导电材料层,所述第一导电材料层的第一部分连接到所述衬底并且在基本上平行于由所述衬底限定的平面的方向上延伸,并且所述第二部分与所述衬底断开并且延伸到 基本上不平行于由衬底限定的平面的方向; 以及在所述第一导电材料层的至少第二部分上形成的传感器材料层,所述传感器材料层具有小于所述第一导电材料层的第一应力的第二应力。 应力形成应力梯度,该应力梯度使第一导电材料层的第二部分和形成在第一导电材料层的第二部分上方的传感器材料层远离衬底弯曲。
    • 79. 发明授权
    • Structure and method for thin film device
    • 薄膜器件的结构和方法
    • US08269221B2
    • 2012-09-18
    • US12011440
    • 2008-01-24
    • Ping MeiAlbert JeansCarl Taussig
    • Ping MeiAlbert JeansCarl Taussig
    • H01L29/786
    • H01L29/42384H01L29/6675H01L29/78645H01L29/7869Y10S438/942
    • Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
    • 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如,在栅电极中具有纳米间隙的薄膜晶体管。 该方法包括提供基底。 然后在衬底上设置多个平行隔开的导电条。 然后将多个薄膜器件层沉积在导电条上。 3D结构设置在多个薄膜器件层上,该结构具有多个不同的高度。 然后蚀刻3D结构和多个薄膜器件层以限定薄膜器件,例如设置在至少一部分导电条上的薄膜晶体管。
    • 80. 发明授权
    • Structure and method for thin film device
    • 薄膜器件的结构和方法
    • US07341893B2
    • 2008-03-11
    • US11144204
    • 2005-06-02
    • Ping MeiAlbert JeansCarl Taussig
    • Ping MeiAlbert JeansCarl Taussig
    • H01L21/00
    • H01L29/42384H01L29/6675H01L29/78645H01L29/7869Y10S438/942
    • Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
    • 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如,在栅电极中具有纳米间隙的薄膜晶体管。 该方法包括提供基底。 然后在衬底上设置多个平行隔开的导电条。 然后将多个薄膜器件层沉积在导电条上。 3D结构设置在多个薄膜器件层上,该结构具有多个不同的高度。 然后蚀刻3D结构和多个薄膜器件层以限定薄膜器件,例如设置在至少一部分导电条上的薄膜晶体管。