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71. 发明授权

US06385667B1 System for configuring a flash memory card with enhanced operating mode detection and user-friendly interfacing system 有权
标题翻译：用于通过监视来自主机的未编码信号和卡中的编码信号来将闪存卡配置到所选操作模式的系统
公开(公告)号：US06385667B1
公开(公告)日：2002-05-07
申请号：US09234430
申请日：1999-01-20
申请人： Petro Estakhri , Mahmud Assar
发明人： Petro Estakhri , Mahmud Assar
IPC分类号： G06F1314
CPC分类号： G11C7/1045 , G06F13/4081 , G11C7/20
摘要： An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.
摘要翻译：一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。接口系统包括接口设备和闪存卡。接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。闪存卡利用五十针连接通过接口设备与主机系统进行接口。闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。这些操作模式中的每一种都需要不同的协议。在使用接口设备进行初始化时，闪存卡会自动检测接口设备的选定操作模式，并配置自身以所选择的操作模式进行操作。通过感测未编码的信号和编码信号来实现操作模式检测。编码信号用有限的一组预定码进行编码。每个预定代码唯一地标识特定的操作模式。

72. 发明授权

US6151247A Method and apparatus for decreasing block write operation times performed on nonvolatile memory 有权
公开(公告)号：US6151247A
公开(公告)日：2000-11-21
申请号：US520904
申请日：2000-03-07
申请人： Petro Estakhri , Berhanu Iman
发明人： Petro Estakhri , Berhanu Iman
IPC分类号： G11C16/02 , G06F3/06 , G06F11/10 , G06F12/00 , G06F12/02 , G11C8/12 , G11C16/08 , G11C16/10 , G11C16/04
CPC分类号： G11C16/102 , G06F12/0246 , G06F3/0616 , G06F3/064 , G06F3/0679 , G11C16/08 , G11C8/12 , G06F11/1068
摘要： In accordance with an embodiment of the present invention, a solid state storage system and method is disclosed for reducing the number of write operations when re-writing a block of information that has been previously written by a host. The system includes a controller coupled to a host and a nonvolatile memory unit for controlling reading and writing of information organized in sectors from and to the nonvolatile memory unit, as commanded by the host. The controller maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit, a block is re-written using a different number of write operations in various alternative embodiments of the present invention. The flag information is indicative of the status of the block such that during power-up, the controller reads the address value and the flag information of a block and determines the status of the block and in accordance therewith finishes re-writing of the block, if necessary and updates the LUT accordingly.

73. 发明授权

US06141249A Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time 有权
标题翻译：在非易失性存储器单元内组织块以有效地减少扇区写入操作时间
公开(公告)号：US06141249A
公开(公告)日：2000-10-31
申请号：US389994
申请日：1999-09-03
申请人： Petro Estakhri , Berhanu Iman
发明人： Petro Estakhri , Berhanu Iman
IPC分类号： G11C16/02 , G06F12/00 , G06F12/06 , G11C7/10 , G11C8/12 , G11C16/08 , G11C16/10 , G11C16/04
CPC分类号： G11C8/12 , G11C16/08 , G11C16/10 , G11C16/102
摘要： An embodiment of the present invention includes a nonvolatile memory system for storing sector information in storage locations within nonvolatile memory organized into blocks, a plurality of blocks defining a super block and each block having a predetermined plurality of sectors. The nonvolatile memory system includes a controller for shifting sector information to a first and a second block of a particular super block and writing sector information to the first block of the particular super block, wherein shifting to the second block occurs entirely during the writing to the first block thereby decreasing the time required to perform write operations to blocks and increasing overall system performance.
摘要翻译：本发明的实施例包括一种非易失性存储器系统，用于将组织成块的非易失性存储器内的存储位置中的扇区信息存储，定义超级块的多个块以及具有预定多个扇区的每个块。非易失性存储器系统包括用于将扇区信息移动到特定超级块的第一和第二块并将扇区信息写入特定超级块的第一块的控制器，其中转移到第二块完全在写入到第二块期间发生第一块，从而减少对块执行写入操作所需的时间并提高整体系统性能。

74. 发明授权

US6134151A Space management for managing high capacity nonvolatile memory 有权
标题翻译：用于管理高容量非易失性存储器的空间管理
公开(公告)号：US6134151A
公开(公告)日：2000-10-17
申请号：US519226
申请日：2000-03-06
申请人： Petro Estakhri , Berhanu Iman , Min Guo
发明人： Petro Estakhri , Berhanu Iman , Min Guo
IPC分类号： G06F12/02 , G11C8/12 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16
CPC分类号： G06F12/0246 , G11C16/04 , G11C16/08 , G11C16/102 , G11C16/16 , G11C8/12
摘要： In accordance with an embodiment of the present invention, a method and apparatus is disclosed for use in a digital system having a host coupled to at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory devices and reads the stored digital information from the nonvolatile memory devices. The memory devices are organized into blocks of sectors of information. The method is for erasing digital information stored in the blocks of the nonvolatile memory devices and comprises assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors. The method further comprises forming `super` blocks, each `super` block comprising a plurality of blocks, identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device for erasure of the particular `super` block and erasing the first and second selected blocks of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second selected blocks, wherein the speed of erase operations in the digital system is substantially increased thereby increasing the overall performance of the digital system.
摘要翻译：根据本发明的实施例，公开了一种在具有耦合到至少两个非易失性存储器件的主机的数字系统中使用的方法和装置。主机将数字信息存储在非易失性存储器件中，并从非易失性存储器件读取所存储的数字信息。存储器件被组织成块信息块。该方法是用于擦除存储在非易失性存储器件的块中的数字信息，并且包括按顺序向每个非易失性存储器件分配预定数量的块，每个块具有预定数量的扇区。该方法还包括形成“超”块，每个“超级”块包括多个块，标识具有至少两个块的特定“超级”块，第一块位于第一非易失性存储器设备中，第二块为位于第二非易失性存储器件中，用于擦除特定“超”块并擦除特定“超级”块的第一和第二选定块，使得执行第二块的擦除而不用等待完成第一个块; 并且在擦除第一和第二所选择的块期间指示第一和第二非易失性存储器件正在占用的状态，其中数字系统中的擦除操作的速度被大大增加，从而增加了数字系统的整体性能。

75. 发明授权

US5586306A Integrated circuit servo system control for computer mass storage device with distributed control functionality to reduce transport delay 失效
标题翻译：用于具有分布式控制功能的计算机大容量存储设备的集成电路伺服系统控制，以减少传输
公开(公告)号：US5586306A
公开(公告)日：1996-12-17
申请号：US448098
申请日：1995-05-23
申请人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
发明人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
IPC分类号： G11B5/55 , G11B5/596 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/08 , G11B21/10 , G11B27/30 , G11B33/10 , G06F3/00
CPC分类号： G11B27/3027 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/083 , G11B21/106 , G11B5/5526 , G11B5/59605 , G11B5/59655 , G11B33/10
摘要： An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.
摘要翻译：集成电路控制计算机大容量存储装置的低级机电功能，例如包括用于可旋转地控制盘的主轴电机的磁盘驱动器和用于相对于盘定位至少一个读/写头的致动器，读取或写入配置在信息数据扇区中的编码数据，并读取伺服数据扇区的编码数据。伺服子系统耦合到读/写头的输出端，用于检测伺服数据扇区并提供响应于此的控制信号。模拟数字子系统还耦合到读/写头的输出端，并响应于伺服子系统控制信号操作，用于将伺服数据扇区的编码数据转换为数字换能器位置信息，该位置信息表示相对于数据轨道的读/写头。数据处理子系统耦合到模数 - 数字子系统，用于处理数字换能器位置信息并响应于此提供数字运动控制信号。数字到模拟子系统耦合到数据处理子系统，用于响应于数字运动控制信号向主轴电动机和致动器提供模拟控制信号。

76. 发明授权

US5140595A Burst mode error detection and definition 失效
标题翻译：突发模式错误检测和定义
公开(公告)号：US5140595A
公开(公告)日：1992-08-18
申请号：US581508
申请日：1990-10-04
申请人： John S. Geldman , Petro Estakhri
发明人： John S. Geldman , Petro Estakhri
IPC分类号： H03M13/17
CPC分类号： H03M13/17
摘要： A network for detection and correction of errors in a digital signal data stream, using an encoded code remainder that augments the data stream. The network utilizes a linear shift feedback register and a data register that works as a shifter or as a counter in assisting the error detection/correction process. Although the digital signal is in the form of serial data, the data register works with bytes, rather than bits, in a parallel arrangement so that the processing time is substantially reduced.
摘要翻译：用于检测和校正数字信号数据流中的错误的网络，使用增加数据流的编码码余数。该网络利用线性移位反馈寄存器和作为移位器或计数器的数据寄存器来辅助错误检测/校正处理。尽管数字信号是串行数据的形式，数据寄存器以并行布置的字节而不是位来工作，从而大大减少了处理时间。

77. 发明授权

US09520174B2 Method and apparatus for writing to a magnetic tunnel junction (MTJ) by applying incrementally increasing voltage level 有权
公开(公告)号：US09520174B2
公开(公告)日：2016-12-13
申请号：US14754635
申请日：2015-06-29
申请人： Ebrahim Abedifard , Petro Estakhri
发明人： Ebrahim Abedifard , Petro Estakhri
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1677 , G11C11/1693 , G11C11/5607
摘要： A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

78. 发明授权

US08554985B2 Memory block identified by group of logical block addresses, storage device with movable sectors, and methods 失效
标题翻译：由逻辑块地址组识别的存储块，具有可移动扇区的存储设备和方法
公开(公告)号：US08554985B2
公开(公告)日：2013-10-08
申请号：US13045159
申请日：2011-03-10
申请人： Petro Estakhri , Berhanu Iman , Ali Ganjuei
发明人： Petro Estakhri , Berhanu Iman , Ali Ganjuei
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/064 , G06F3/0679 , G06F11/1008 , G06F11/1068 , G06F12/023 , G06F2212/7201 , G11C8/12 , G11C16/08 , G11C16/102 , G11C29/765 , G11C29/82
摘要： In an embodiment, a non-volatile memory has erasable blocks of memory cells. The one or more of the erasable blocks include a particular block to be identified by a particular group of logical block addresses corresponding to a predetermined group of sectors.
摘要翻译：在一个实施例中，非易失性存储器具有可擦除存储器单元块。一个或多个可擦除块包括要由对应于预定扇区组的特定组的逻辑块地址识别的特定块。

79. 发明授权

US08078797B2 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices 有权
标题翻译：通过将扇区同时写入多个闪存设备来提高闪存设备的存储性能
公开(公告)号：US08078797B2
公开(公告)日：2011-12-13
申请号：US12470944
申请日：2009-05-22
申请人： Petro Estakhri , Berhanu Iman
发明人： Petro Estakhri , Berhanu Iman
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0238 , G06F3/0613 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F12/0246 , G11C16/08 , G11C16/102 , G11C29/765 , G11C29/82
摘要： A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the memory unit are organized into one or more sub-blocks configured to store sectors of information from a host. The sectors of information can be identified by sector numbers of a predetermined order. The memory control circuitry is configured to write a sector of information to a location of a particular sub-block of a particular block. The memory control circuitry is further configured to write a sector of information to a location of a sub-block of the particular block that is other than the particular sub-block, regardless of the predetermined order of the sector numbers of the sectors of information. The memory control circuitry is further configured to write the sectors of information to the locations of the sub-blocks of the particular block substantially concurrently.
摘要翻译：实施例的存储器存储系统包括耦合到存储器单元的非易失性存储器单元和存储器控制电路。存储器单元的存储位置被组织成被配置为存储来自主机的信息扇区的一个或多个子块。可以通过预定顺序的扇区号来识别信息扇区。存储器控制电路被配置为将信息扇区写入特定块的特定子块的位置。存储器控制电路还被配置为将信息扇区写入除了特定子块之外的特定块的子块的位置，而不管信息扇区的扇区号的预定顺序如何。存储器控制电路还被配置为基本上同时地将信息扇区写入特定块的子块的位置。

80. 发明授权

US08073986B2 Memory devices configured to identify an operating mode 有权
标题翻译：配置为识别操作模式的内存设备
公开(公告)号：US08073986B2
公开(公告)日：2011-12-06
申请号：US12782232
申请日：2010-05-18
申请人： Petro Estakhri , Mahmud Assar
发明人： Petro Estakhri , Mahmud Assar
IPC分类号： G06F3/00
CPC分类号： G11C7/1045 , G06F13/4081 , G11C7/20
摘要： Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.
摘要翻译：具有存储器模块，接口，识别电路和耦合到存储器模块和识别电路的控制器的存储器件。识别电路被配置为响应于先前通过识别电路施加到接口的多个信号，从在接口处感测到的多个信号中识别所选择的操作模式。控制器可操作以响应于识别电路将存储器件配置为所选择的操作模式。

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