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71. 发明授权

US07740493B2 Universal serial bus (USB) flash drive housing a slim USB device and having swivel cap functionalities allowing for two locking positions 失效
标题翻译：通用串行总线（USB）闪存驱动器，内置超薄USB设备，并具有允许两个锁定位置的旋转盖功能
公开(公告)号：US07740493B2
公开(公告)日：2010-06-22
申请号：US11874108
申请日：2007-10-17
申请人： Jim Chin-Nan Ni , David Nguyen , I-Kang Yu , Abraham Chih-Kang Ma
发明人： Jim Chin-Nan Ni , David Nguyen , I-Kang Yu , Abraham Chih-Kang Ma
IPC分类号： H01R13/44
CPC分类号： H01R13/453 , H05K5/0278 , Y10T29/49002
摘要： A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end and a swivel cap having a side slit that serves as an opening into which the slim USB device travels horizontally, the side slit being disposed along a lateral side of the swivel cap. The USB flash drive also includes a USB device rivet placed into the slim USB device and the swivel cap to pivotally connect them at one of the ends of the slim USB device, so that the slim USB device is pivotally extendable outwardly from the side slit in a closed or open position. The swivel rocker is pivotally extendable outwardly from the opposite end of the slim USB device and when the swivel rocker is extended outwardly, the slim USB device is caused to extend outwardly.
摘要翻译：通用串行总线（USB）闪存驱动器包括一个细长的USB设备，其具有用于将USB闪存驱动器耦合到主机和相对端的端部，以及具有用作开口的侧面狭缝的旋转盖，其中该超薄USB设备水平移动，侧缝沿旋转盖的侧面设置。 USB闪存驱动器还包括放置在细长USB设备中的USB设备铆钉和旋转盖，以在超薄USB设备的一端的一端枢轴连接，使得细长的USB设备可从侧缝中向外可枢转地延伸关闭或打开位置。旋转摇杆从细长的USB装置的相对端向外可枢转地延伸，并且当旋转摇杆向外延伸时，使细长的USB装置向外延伸。

72. 发明授权

US07544073B2 Universal serial bus (USB) flash drive with swivel cap functionalities with two locking positions 失效
标题翻译：通用串行总线（USB）闪存驱动器，带有两个锁定位置的旋转盖功能
公开(公告)号：US07544073B2
公开(公告)日：2009-06-09
申请号：US11927484
申请日：2007-10-29
申请人： David Nguyen , Jim Chin-Nan Ni , Charles Chung Lee , Abraham Chih-Kang Ma
发明人： David Nguyen , Jim Chin-Nan Ni , Charles Chung Lee , Abraham Chih-Kang Ma
IPC分类号： H01R13/44
CPC分类号： H01R13/447 , G06K19/07732 , H01R13/504 , H05K5/0278 , Y10T29/49002
摘要： A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs.
摘要翻译：通用串行总线（USB）闪存驱动器包括具有用于将USB闪存驱动器耦合到主机和相对端的端部的细长USB设备，以及设置在两个盖上的具有圆切口的旋转“带状”金属盖腿卡扣联接圆附件允许旋转盖基本上旋转到第一和第二锁定位置并围绕USB装置的z轴大致旋转360度。当卡扣槽对准卡扣锁定片顶部时，金属盖通常处于锁定位置，使得突起卡环向下下降直到定位件与卡锁槽相对。当解锁时，突起卡环被提起并搁置在两个卡扣卡扣上。

73. 发明授权

US07496709B2 Integrated circuit memory device having delayed write timing based on read response time 有权
标题翻译：具有基于读取响应时间的延迟写入定时的集成电路存储器件
公开(公告)号：US07496709B2
公开(公告)日：2009-02-24
申请号：US11953803
申请日：2007-12-10
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

74. 发明申请

US20080278902A1 Universal Serial Bus (USB) Flash Drive with Swivel Cap Functionalities with Two Locking Positions 失效
标题翻译：具有两个锁定位置的旋转盖功能的通用串行总线（USB）闪存驱动器
公开(公告)号：US20080278902A1
公开(公告)日：2008-11-13
申请号：US11927484
申请日：2007-10-29
申请人： David Nguyen , Jim Chin-Nan Ni , Charles Chung Lee , Abraham Chih-Kang Ma
发明人： David Nguyen , Jim Chin-Nan Ni , Charles Chung Lee , Abraham Chih-Kang Ma
IPC分类号： G06F1/16 , H01S4/00
CPC分类号： H01R13/447 , G06K19/07732 , H01R13/504 , H05K5/0278 , Y10T29/49002
摘要： A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs.
摘要翻译：通用串行总线（USB）闪存驱动器包括具有用于将USB闪存驱动器耦合到主机和相对端的端部的细长USB设备，以及设置在两个盖上的具有圆切口的旋转“带状”金属盖腿卡扣联接圆附件允许旋转盖基本上旋转到第一和第二锁定位置并围绕USB装置的z轴大致旋转360度。当卡扣槽对准卡扣锁定片顶部时，金属盖通常处于锁定位置，使得突起卡环向下下降直到定位件与卡锁槽相对。当解锁时，突起卡环被提起并搁置在两个卡扣卡扣上。

75. 发明授权

US07360050B2 Integrated circuit memory device having delayed write capability 失效
标题翻译：具有延迟写入能力的集成电路存储器件
公开(公告)号：US07360050B2
公开(公告)日：2008-04-15
申请号：US11681375
申请日：2007-03-02
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.
摘要翻译：集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

76. 发明申请

US20070198868A1 Memory System Having Delayed Write Timing 有权
标题翻译：具有延迟写入时序的存储器系统
公开(公告)号：US20070198868A1
公开(公告)日：2007-08-23
申请号：US11692162
申请日：2007-03-27
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： H04L7/033
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.
摘要翻译：存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。第二个互连传送写入命令和读取命令。第三个互连传送写入数据和读取数据。集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。

77. 发明授权

US07236894B2 Circuits, systems and methods for dynamic reference voltage calibration 有权
标题翻译：用于动态参考电压校准的电路，系统和方法
公开(公告)号：US07236894B2
公开(公告)日：2007-06-26
申请号：US11021598
申请日：2004-12-23
申请人： Kyung Suk Oh , Frank Lambrecht , David Nguyen
发明人： Kyung Suk Oh , Frank Lambrecht , David Nguyen
IPC分类号： G11C7/14
CPC分类号： G11C5/147 , G01R31/31924 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A circuit, system and method adjusts a reference voltage, such as an internal or external reference voltage VREF, in response to a first voltage at a first contact, such as a pin on a memory controller used for reading or writing data, and a second voltage at a second contact in embodiments. Logic is coupled to the first and second contacts to provide a control signal in response to the first and second voltages. A comparator provides an input signal to the logic in response to a target reference voltage and the reference voltage during a calibration or initialization mode of operation. In an alternate embodiment, a plurality of data values at a first contact are compared to a predetermined plurality of test data. An up/down signal is then provided to a counter and a register stores a counter value used to provide a reference voltage.
摘要翻译：电路，系统和方法响应于第一触点处的第一电压（例如用于存储器控制器的存储器控制器中的引脚）来调整参考电压，诸如内部或外部参考电压V REF，读取或写入数据，以及第二触点的第二电压。逻辑耦合到第一和第二触点以响应于第一和第二电压提供控制信号。比较器在校准或初始化操作模式期间响应于目标参考电压和参考电压向逻辑器提供输入信号。在替代实施例中，将第一联系人处的多个数据值与预定的多个测试数据进行比较。然后向计数器提供上/下信号，并且寄存器存储用于提供参考电压的计数器值。

78. 发明申请

US20070120575A1 Multiple Channel Modules and Bus Systems Using Same 审中-公开
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US20070120575A1
公开(公告)日：2007-05-31
申请号：US11668422
申请日：2007-01-29
申请人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
发明人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
IPC分类号： H03K17/16 , G11C5/00
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

79. 发明申请

US20070023248A1 CLUTCH ASSEMBLY 审中-公开
标题翻译：离合器总成
公开(公告)号：US20070023248A1
公开(公告)日：2007-02-01
申请号：US11461536
申请日：2006-08-01
申请人： David Nguyen , John Hayward
发明人： David Nguyen , John Hayward
IPC分类号： F16D41/08
CPC分类号： F16D41/069 , F16D41/084
摘要： A clutch assembly that includes an input member rotatable about an axis, an output member rotatable about the axis, and an engagement member having a portion between the input and output members. The engagement member is operable to selectively couple the input and output members together for co-rotation. The clutch assembly further includes a blocking member having a base and a projection. The projection is coupled to the engagement member to substantially prevent the engagement member from coupling the input and output members together for co-rotation when the input member rotates in a first direction relative to the output member, while allowing the engagement member to couple the input and output members lor together co-rotation when the input member rotates in a second direction relative to the output member.
摘要翻译：一种离合器组件，其包括可围绕轴线旋转的输入构件，可围绕该轴线旋转的输出构件以及具有在输入和输出构件之间的部分的接合构件。接合构件可操作以选择性地将输入和输出构件联接在一起用于共同旋转。离合器组件还包括具有基部和突起的阻挡构件。当输入构件相对于输出构件沿第一方向旋转时，凸起联接到接合构件以基本上防止接合构件将输入和输出构件联接在一起用于共同旋转，同时允许接合构件将输入并且当输入构件相对于输出构件沿第二方向旋转时，输出构件一起共同旋转。

80. 发明授权

US07162376B2 Circuits, systems and methods for dynamic reference voltage calibration 有权
标题翻译：用于动态参考电压校准的电路，系统和方法
公开(公告)号：US07162376B2
公开(公告)日：2007-01-09
申请号：US11063490
申请日：2005-02-22
申请人： Kyung Suk Oh , Frank Lambrecht , David Nguyen
发明人： Kyung Suk Oh , Frank Lambrecht , David Nguyen
IPC分类号： G11C7/14
CPC分类号： G11C5/147 , G01R31/31924 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A system comprises a master device and a plurality of memory devices coupled to the master device by an interconnect in an embodiment. The master device obtains a plurality of values representing reference voltage values and selects a first value in the plurality of values representing reference voltage values to generate an internal reference voltage value when reading data from a selected memory device in the plurality of memory devices. A method comprises obtaining a plurality of values representing reference voltages for a plurality of memory devices in an embodiment. A first value is selected in the plurality of values representing reference voltages. A reference voltage value is adjusted in response to the first value to an adjusted reference voltage value. Data is transferred to a selected memory device in the plurality of memory devices using the adjusted reference voltage value.
摘要翻译：在一个实施例中，系统包括主设备和通过互连耦合到主设备的多个存储设备。主装置获取表示参考电压值的多个值，并且在从多个存储装置中的选定存储装置读取数据时，选择表示参考电压值的多个值中的第一值以产生内部参考电压值。一种方法包括在一个实施例中获得表示多个存储器件的参考电压的多个值。在表示参考电压的多个值中选择第一值。响应于第一值将参考电压值调整到调整的参考电压值。使用经调整的参考电压值将数据传送到多个存储器件中的选定的存储器件。

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