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1. 发明申请

US20070120575A1 Multiple Channel Modules and Bus Systems Using Same 审中-公开
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US20070120575A1
公开(公告)日：2007-05-31
申请号：US11668422
申请日：2007-01-29
申请人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
发明人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
IPC分类号： H03K17/16 , G11C5/00
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

2. 发明申请

US20050142950A1 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US20050142950A1
公开(公告)日：2005-06-30
申请号：US11054955
申请日：2005-02-11
申请人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
发明人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
IPC分类号： G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14 , H01R24/00
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

3. 发明申请

US20070220188A1 Expandable Slave Device System with Buffered Subsystems 有权
标题翻译：具有缓冲子系统的可扩展从设备系统
公开(公告)号：US20070220188A1
公开(公告)日：2007-09-20
申请号：US11752242
申请日：2007-05-22
申请人： Bruno Garlepp , Richard Barth , Kevin Donnelly , Ely Tsern , Craig Hampel , Jeffrey Mitchell , James Gasbarro , Billy Garrett , Fredrick Ware , Donald Perino
发明人： Bruno Garlepp , Richard Barth , Kevin Donnelly , Ely Tsern , Craig Hampel , Jeffrey Mitchell , James Gasbarro , Billy Garrett , Fredrick Ware , Donald Perino
IPC分类号： G06F13/14
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.
摘要翻译：系统包括第一总线，耦合到第一总线的主设备和耦合到第一总线的一个或多个子系统。相应的子系统包括第二总线，耦合到第二总线的一个或多个从设备，写入缓冲器，用于经由第一总线接收来自主设备的输入信号，以及经由第二总线将信号发送到一个或多个从设备响应于输入信号，以及读缓冲器，用于经由第二总线接收来自一个或多个从设备的输出信号，并响应于输出信号经由第一总线向主设备发送信号。

4. 发明申请

US20070247935A1 Clocked Memory System with Termination Component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US20070247935A1
公开(公告)日：2007-10-25
申请号：US11767983
申请日：2007-06-25
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

5. 发明申请

US20050132158A1 Memory device signaling system and method with independent timing calibration for parallel signal paths 有权
标题翻译：用于并行信号路径的独立定时校准的存储器件信号系统和方法
公开(公告)号：US20050132158A1
公开(公告)日：2005-06-16
申请号：US11039447
申请日：2005-01-18
申请人： Craig Hampel , Richard Perego , Stefanos Sidiropoulos , Ely Tsern , Fredrick Ware
发明人： Craig Hampel , Richard Perego , Stefanos Sidiropoulos , Ely Tsern , Fredrick Ware
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4078 , H04L7/00 , G06F12/00
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.
摘要翻译：存储器系统包括彼此耦合的存储器控制器和存储器组件。存储器控制器包括用于从存储器组件接收第一信号和第二信号的接口，其中第一信号包括第一符号，第二信号包括第二符号。存储器控制器的第一电路通过使用相对于参考时钟信号的第一定时偏移对第一符号进行采样来接收第一信号，并且存储器控制器的第二电路通过使用第二定时偏移量对第二符号进行采样来接收第二信号相对于参考时钟信号。第一定时偏移与第二定时偏移无关。

6. 发明申请

US20060236031A1 Upgradable memory system with reconfigurable interconnect 有权
公开(公告)号：US20060236031A1
公开(公告)日：2006-10-19
申请号：US11388449
申请日：2006-03-24
申请人： Richard Perego , Frederick Ware , Ely Tsern , Craig Hampel
发明人： Richard Perego , Frederick Ware , Ely Tsern , Craig Hampel
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

7. 发明申请

US20060069895A1 Method, system and memory controller utilizing adjustable write data delay settings 有权
标题翻译：方法，系统和内存控制器利用可调写入数据延迟设置
公开(公告)号：US20060069895A1
公开(公告)日：2006-03-30
申请号：US11281184
申请日：2005-11-15
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
摘要翻译：一种使用可调写入数据延迟设置的方法，系统和存储器控制器。存储器控制器包括控制发射电路，数据发射电路和定时电路。控制电路通过共享控制信号路径将控制信号发送到多个存储器件。数据发送电路经由各自的数据信号路径向存储器件发送数据信号。定时电路延迟每个数据信号路径上的数据信号的传输相应的时间间隔，该时间间隔至少部分地基于控制信号在从存储器控制器到控制信号路径的传播所需的时间相应的一个存储器件。

8. 发明申请

US20050169097A1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于在不同位置的存储器组件之间协调存储器操作的方法和装置
公开(公告)号：US20050169097A1
公开(公告)日：2005-08-04
申请号：US11094137
申请日：2005-03-31
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G06F12/00 , G06F13/16 , G06F13/40 , G06F13/42 , G11C8/00 , G11C11/401 , G11C29/00 , G11C29/02
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the present disclosure, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译：描述了用于协调不同位置的存储器组件之间的存储器操作的方法和装置。根据本公开的实施例，对耦合到多个存储器组件的地址总线实现波浪流水线化。多个存储器组件根据与地址总线传播延迟和数据总线传播延迟有关的坐标进行配置。与复制这些信号的传播延迟的地址和/或控制信号相关联的定时信号用于协调存储器操作。

9. 发明申请

US20060077731A1 Memory module with termination component 有权
公开(公告)号：US20060077731A1
公开(公告)日：2006-04-13
申请号：US11280560
申请日：2005-11-15
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.

10. 发明申请

US20060039174A1 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US20060039174A1
公开(公告)日：2006-02-23
申请号：US11219096
申请日：2005-09-01
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.
摘要翻译：一种具有端接部件的存储器模块。存储器模块包括多个存储器件，终端元件，控制信号路径和多个数据信号路径。控制信号路径被耦合到每个存储器件和终端元件，并且沿着存储器件延伸，使得在控制信号路径上传播的信号在到达终端元件之前连续传播通过每个存储器件。一组唯一的数据信号路径耦合到每个存储器件。

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