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71. 发明授权

US07904868B2 Structures including means for lateral current carrying capability improvement in semiconductor devices 有权
标题翻译：结构包括用于半导体器件中横向电流承载能力改进的装置
公开(公告)号：US07904868B2
公开(公告)日：2011-03-08
申请号：US11873711
申请日：2007-10-17
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：包括半导体结构的设计结构。半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

72. 发明申请

US20100327958A1 Leakage Current Mitigation in a Semiconductor Device 有权
标题翻译：半导体器件漏电流减轻
公开(公告)号：US20100327958A1
公开(公告)日：2010-12-30
申请号：US12494460
申请日：2009-06-30
申请人： Jong-Ru Guo , Louis Lu-Chen Hsu , Rajiv Vasant Joshi , Ping-Chuan Wang , Zhijian Yang
发明人： Jong-Ru Guo , Louis Lu-Chen Hsu , Rajiv Vasant Joshi , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03K3/01 , G01R31/26
CPC分类号： H03K17/0822
摘要： A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.
摘要翻译：识别泄漏电流目标单元内的休眠模式目标半导体器件，以减轻漏电流，防止其达到灾难性的失控。泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点，并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流，并测量所收集的漏电流之间的差异。比较器接收并比较当前移位监视器单元和参考电压发生器的输出。当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时，比较器将报警信号传播到泄漏电流目标单元，表示泄漏电流即将接近灾难性失控水平的条件。该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式，其包括施加到目标半导体器件的栅极的修复电压发生器的修复电压。

73. 发明授权

US07790599B2 Metal cap for interconnect structures 有权
标题翻译：用于互连结构的金属盖
公开(公告)号：US07790599B2
公开(公告)日：2010-09-07
申请号：US11734958
申请日：2007-04-13
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76843 , H01L21/76849
摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.
摘要翻译：描述了形成用于互连结构的改进的金属帽的结构和方法。该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

74. 发明申请

US20100210043A1 IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA 有权
标题翻译：通过硅片的在线深度测量
公开(公告)号：US20100210043A1
公开(公告)日：2010-08-19
申请号：US12371724
申请日：2009-02-16
申请人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
发明人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
摘要翻译：在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构，设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。在制造期间同时产生电阻测量沟槽结构和未填充TSV。

75. 发明申请

US20100182041A1 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA 有权
标题翻译：具有通过硅保险丝的3D芯片堆叠
公开(公告)号：US20100182041A1
公开(公告)日：2010-07-22
申请号：US12357664
申请日：2009-01-22
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03K19/173 , H01L29/00 , H01L29/40 , H01L21/44 , H01L23/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/3011 , H01L2924/00014
摘要： Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
摘要翻译：硅芯片中的可编程熔丝式硅通孔（TSV）在同一芯片中提供非可编程TSV。可编程保险丝型TSV可以采用TSV结构内的区域，其具有侧壁间隔件，其限制邻近芯片表面接触焊盘的TSV的横截面导电路径。通过编程电路施加足够的电流导致金属的电迁移，从而在接触焊盘中产生空隙，并因此产生开路。编程可以由多层芯片堆叠中的两个相邻芯片上的互补电路来执行。

76. 发明申请

US20100182040A1 PROGRAMMABLE THROUGH SILICON VIA 有权
标题翻译：可通过硅可编程
公开(公告)号：US20100182040A1
公开(公告)日：2010-07-22
申请号：US12357659
申请日：2009-01-22
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03K19/173 , H01L29/00 , H01L29/40 , H01L21/44 , H01L23/02
CPC分类号： H01L23/5252 , H01L21/76898 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/50 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05573 , H01L2224/05611 , H01L2224/08146 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/10253 , H01L2924/3011 , H01L2924/00 , H01L2224/05624 , H01L2924/00014 , H01L2224/05647 , H01L2224/05684
摘要： Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
摘要翻译：硅芯片中的硅通孔（TSV）都是可编程的和不可编程的。可编程TSV可以使用金属/绝缘体/金属结构从开放状态切换到短路状态，并且通过在多层芯片堆叠中的两个相邻芯片上的互补电路进行编程。

77. 发明授权

US07701015B2 Bipolar and CMOS integration with reduced contact height 失效
标题翻译：双极和CMOS集成，降低接触高度
公开(公告)号：US07701015B2
公开(公告)日：2010-04-20
申请号：US10596573
申请日：2003-12-16
申请人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
发明人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
IPC分类号： H01L29/72
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/8249 , H01L23/485 , H01L23/5389 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
摘要翻译：公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。垂直双极晶体管比CMOS晶体管更高的器件。在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。布线层位于钝化层的上方。垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

78. 发明申请

US20100038747A1 ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD 有权
标题翻译：电可编程保险丝和制造方法
公开(公告)号：US20100038747A1
公开(公告)日：2010-02-18
申请号：US12192387
申请日：2008-08-15
申请人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
发明人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.
摘要翻译：电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近阴极和熔断体连接处的连接处。

79. 发明授权

US07569475B2 Interconnect structure having enhanced electromigration reliability and a method of fabricating same 有权
标题翻译：具有增强的电迁移可靠性的互连结构及其制造方法
公开(公告)号：US07569475B2
公开(公告)日：2009-08-04
申请号：US11560044
申请日：2006-11-15
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
摘要翻译：提供了具有改进的电迁移（EM）可靠性的互连结构。本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散屏障相邻。在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

80. 发明申请

US20090167336A1 METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS 失效
标题翻译：用于动态表征可靠性磨损机制的方法和装置
公开(公告)号：US20090167336A1
公开(公告)日：2009-07-02
申请号：US11968444
申请日：2008-01-02
申请人： Giuseppe La Rosa , Kevin Kolvenbach , Ping-Chuan Wang , Stephen D. Wyatt
发明人： Giuseppe La Rosa , Kevin Kolvenbach , Ping-Chuan Wang , Stephen D. Wyatt
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2856
摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.
摘要翻译：公开了用于动态表征可靠性损耗机制的方法和装置。该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止向被测器件输入波形的结构，用于测量一个或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。

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