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71. 发明授权

US08735960B2 High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance 有权
标题翻译：高紫外光吸收氧氮化硅薄膜，用于改善闪存器件性能
公开(公告)号：US08735960B2
公开(公告)日：2014-05-27
申请号：US12313134
申请日：2008-11-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L23/485 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
摘要翻译：紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

72. 发明申请

US20110169069A1 HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE 有权
标题翻译：用于存储器件的HTO偏移和BL转换处理以提高器件性能
公开(公告)号：US20110169069A1
公开(公告)日：2011-07-14
申请号：US13069710
申请日：2011-03-23
申请人： Ning Cheng , Huaqiang Wu , Hiro Kinoshita , Jihwan Choi
发明人： Ning Cheng , Huaqiang Wu , Hiro Kinoshita , Jihwan Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11565 , H01L27/11568 , H01L29/7923
摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
摘要翻译：提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

73. 发明授权

US07943983B2 HTO offset spacers and dip off process to define junction 有权
标题翻译： HTO偏移间隔物和浸渍过程来界定结
公开(公告)号：US07943983B2
公开(公告)日：2011-05-17
申请号：US12342011
申请日：2008-12-22
申请人： Huaqiang Wu , Hiro Kinoshita , Ning Cheng , Arturo Ruiz , Jihwan Choi
发明人： Huaqiang Wu , Hiro Kinoshita , Ning Cheng , Arturo Ruiz , Jihwan Choi
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/823425 , H01L29/66833
摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.
摘要翻译：提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。存储单元包含一对第一位线和一对第二位线。可以通过使用彼此具有不同横向长度的第一和第二间隔件的注入工艺来形成第一和第二位线。间隔物可以用于偏移植入物，从而控制位线的横向长度。

74. 发明授权

US07899043B2 Route servicing device, method and system applying the device 有权
标题翻译：路由维护设备，应用设备的方法和系统
公开(公告)号：US07899043B2
公开(公告)日：2011-03-01
申请号：US10582980
申请日：2004-06-22
申请人： Xianli Hu , Rujun Li , Ning Cheng , Haipeng Li
发明人： Xianli Hu , Rujun Li , Ning Cheng , Haipeng Li
IPC分类号： H04L12/28
CPC分类号： H04L45/04 , H04L45/00 , H04L45/02
摘要： The present invention discloses a route service device and a method and a system for realizing call route by the device, in which, route service device and soft switch control device are networked in a layered way, the soft switch control device is the node of the lowest layer, when the user route changes, the soft switch control device reports route information including user node to the father node; the route service device performs registration, and broadcasts the changed route information to the father node, each related route service device performs registration and broadcast by the same way; when calling across domains, the soft switch control device where the calling locates initiates inquiry toward the father node, and receives the returned inquiring result, therefore routing the call to the soft switch control device where the called locates. The present invention employs route service device to replace soft switch control device for performing call route function, therefore enabling the soft switch control device absorbed in providing services, and also providing a scheme of large scale networking at telecommunication level for soft switch control device.
摘要翻译：本发明公开了一种路由服务设备和方法和系统，用于通过设备实现呼叫路由，其中路由服务设备和软交换控制设备以分层方式联网，软交换控制设备为最低层，当用户路由改变时，软交换控制设备向父节点报告包括用户节点的路由信息; 路由服务设备执行注册，并将更改的路由信息广播到父节点，每个相关路由服务设备以相同的方式进行注册和广播; 当通过域呼叫时，呼叫所在的软交换控制设备向父节点发起询问，并接收返回的查询结果，从而将呼叫路由到被叫所在的软交换控制设备。本发明采用路由业务装置来代替软交换控制装置，用于执行呼叫路由功能，从而使得软交换控制装置能够吸收提供业务，并为软交换控制装置提供电信级大规模组网方案。

75. 发明申请

US20100155785A1 HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION 有权
标题翻译： HTO偏移距离和切换过程来定义连接
公开(公告)号：US20100155785A1
公开(公告)日：2010-06-24
申请号：US12342011
申请日：2008-12-22
申请人： Huaqiang Wu , Hiro Kinoshita , Ning Cheng , Arturo Ruiz , Jihwan Choi
发明人： Huaqiang Wu , Hiro Kinoshita , Ning Cheng , Arturo Ruiz , Jihwan Choi
IPC分类号： H01L27/085 , H01L21/4763 , H01L29/78
CPC分类号： H01L27/11568 , H01L21/823425 , H01L29/66833
摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.
摘要翻译：提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质。存储单元包含一对第一位线和一对第二位线。可以通过使用彼此具有不同横向长度的第一和第二间隔件的注入工艺来形成第一和第二位线。间隔物可以用于偏移植入物，从而控制位线的横向长度。

76. 发明申请

US20090101963A1 SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS 有权
标题翻译：分离式充电储存装置内部空间过程
公开(公告)号：US20090101963A1
公开(公告)日：2009-04-23
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

77. 发明申请

US20080079062A1 DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20080079062A1
公开(公告)日：2008-04-03
申请号：US11538404
申请日：2006-10-03
申请人： Amol Ramesh Joshi , Ning Cheng , Minghao Shen
发明人： Amol Ramesh Joshi , Ning Cheng , Minghao Shen
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L29/7923
摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

78. 发明授权

US07238571B1 Non-volatile memory device with increased reliability 有权
标题翻译：非易失性存储器件具有更高的可靠性
公开(公告)号：US07238571B1
公开(公告)日：2007-07-03
申请号：US11063560
申请日：2005-02-24
申请人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
发明人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
摘要翻译：存储器件可以包括多个存储器单元，形成在存储器单元上的第一层间电介质和形成在层间电介质上的至少一个金属层。介电层可以形成在金属层的上方。电介质层可以表示在存储器件的上表面处或附近形成的覆盖层，并且可以在相对低的温度下沉积。

79. 发明授权

US08644708B2 Coupled seed light injection for wavelength division multiplexing passive optical networks 有权
标题翻译：耦合种子光注入用于波分复用无源光网络
公开(公告)号：US08644708B2
公开(公告)日：2014-02-04
申请号：US12901131
申请日：2010-10-08
申请人： Ning Cheng
发明人： Ning Cheng
IPC分类号： H04J14/00 , H04J14/02
CPC分类号： H04J14/02 , H04J3/1694
摘要： An apparatus comprising a first optical transmitter configured to couple to a second optical transmitter, a first optical receiver, and a seed light source, wherein the first optical transmitter and the first optical receiver are part of a first passive optical network (PON) and the second optical transmitter and a second optical receiver are part of a second PON, and wherein at least one of the first optical transmitter and the second optical transmitter is an injection locked laser transmitter. Also disclosed is a method comprising feeding a seed light to a plurality of injection locked laser transmitters in a plurality of PONs using only one broadband light source (BLS), wherein each PON comprises an optical line terminal (OLT) transmitter and a plurality of optical network units (ONUs) transmitters.
摘要翻译：一种装置，包括被配置为耦合到第二光发射器，第一光接收器和种子光源的第一光发射器，其中第一光发射器和第一光接收器是第一无源光网络（PON）的一部分，并且第二光发射机和第二光接收机是第二PON的一部分，并且其中第一光发射机和第二光发射机中的至少一个是注入锁定激光发射机。还公开了一种方法，其包括使用仅一个宽带光源（BLS）将种子光馈送到多个PON中的多个注入锁定的激光发射机，其中每个PON包括光线路终端（OLT）发射机和多个光网络单元（ONU）发射机。

80. 发明授权

US07927723B1 Film stacks to prevent UV-induced device damage 有权
标题翻译：电影堆叠以防止紫外线引起的设备损坏
公开(公告)号：US07927723B1
公开(公告)日：2011-04-19
申请号：US11091524
申请日：2005-03-29
申请人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
发明人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
IPC分类号： G02B1/10 , G02B5/28 , B32B9/00 , B32B19/00
CPC分类号： G02B5/208
摘要： A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.
摘要翻译：膜堆叠包括在一个或多个器件上形成的层间电介质。薄膜叠层还包括形成在层间电介质上的具有高消光系数的第一层和形成在第一层上的具有低消光系数的第二层。第一层和第二层防止对一种或多种设备的紫外线诱发的损坏，同时最小化光刻工艺的反射率。

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