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71. 发明申请

US20120139014A1 STRUCTURE AND METHOD FOR LOW TEMPERATURE GATE STACK FOR ADVANCED SUBSTRATES 审中-公开
标题翻译：用于高级基板的低温门架的结构和方法
公开(公告)号：US20120139014A1
公开(公告)日：2012-06-07
申请号：US12958354
申请日：2010-12-01
申请人： Stephen W. Bedell , Sivananda Kanakasabapathy , Vijay Narayanan
发明人： Stephen W. Bedell , Sivananda Kanakasabapathy , Vijay Narayanan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/28255 , H01L29/1054 , H01L29/4966 , H01L29/517 , H01L29/66477 , H01L29/665
摘要： A low-temperature metal gate stack for a field-effect transistor that is electrically activated at temperatures below 1000° C. The metal gate stack is composed of low melting materials that can be deposited by physical vapor deposition (PVD) onto a substrate.
摘要翻译：用于场效应晶体管的低温金属栅极堆叠，其在低于1000℃的温度下被电活化。金属栅极堆叠由可以通过物理气相沉积（PVD）沉积到衬底上的低熔点材料构成。

72. 发明申请

US20120074533A1 Structures And Techniques For Atomic Layer Deposition 有权
标题翻译：原子层沉积的结构和技术
公开(公告)号：US20120074533A1
公开(公告)日：2012-03-29
申请号：US12890051
申请日：2010-09-24
申请人： Shintaro Aoyama , Robert D. Clark , Steven P. Consiglio , Marinus Hopstaken , Hemanth Jagannathan , Paul Charles Jamison , Gert Leusink , Barry Paul Linder , Vijay Narayanan , Cory Wajda
发明人： Shintaro Aoyama , Robert D. Clark , Steven P. Consiglio , Marinus Hopstaken , Hemanth Jagannathan , Paul Charles Jamison , Gert Leusink , Barry Paul Linder , Vijay Narayanan , Cory Wajda
IPC分类号： H01L29/51 , B32B15/04 , B05D5/12
CPC分类号： H01L21/02181 , B32B15/04 , B32B2457/14 , C23C16/40 , C23C16/401 , C23C16/405 , C23C16/45527 , C23C16/45531 , C23C16/56 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/28194 , H01L29/517
摘要： In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.
摘要翻译：在一个示例性实施例中，一种方法包括：通过执行原子层沉积的第一多个循环，在衬底的表面上形成至少一个第一材料的第一单层; 之后，在第一惰性气氛下，在约650℃至约900℃的第一温度下退火所形成的至少一个第一材料的第一单层; 此后，通过执行第二多个原子层沉积循环形成第二材料的至少一个第二单层，其中所形成的至少一个第二单层的第二材料至少部分地覆盖所述退火的至少一个第一单层第一材料; 然后在第二惰性气氛下，在约650℃和约900℃之间的第二温度下对所形成的至少一个第二单层第二材料进行退火。

73. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

74. 发明授权

US07943460B2 High-K metal gate CMOS 有权
标题翻译：高K金属门CMOS
公开(公告)号：US07943460B2
公开(公告)日：2011-05-17
申请号：US12426457
申请日：2009-04-20
申请人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
发明人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
摘要翻译：提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

75. 发明授权

US07872317B2 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US07872317B2
公开(公告)日：2011-01-18
申请号：US12508177
申请日：2009-07-23
申请人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/70
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

76. 发明授权

US07863126B2 Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region 有权
标题翻译：在PFET区域中制造具有氧化铝层的高k电介质层的CMOS结构
公开(公告)号：US07863126B2
公开(公告)日：2011-01-04
申请号：US12120658
申请日：2008-05-15
申请人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/441
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
摘要翻译：公开了一种用于制造CMOS结构的方法。该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。之后是在NFET器件和PFET器件上的Al层的覆盖布置。该方法还包括在Al层上共享的栅极金属层的布置布置。当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

77. 发明授权

US07858500B2 Low threshold voltage semiconductor device with dual threshold voltage control means 有权
标题翻译：具有双阈值电压控制装置的低阈值电压半导体器件
公开(公告)号：US07858500B2
公开(公告)日：2010-12-28
申请号：US12062972
申请日：2008-04-04
申请人： Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
发明人： Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
IPC分类号： H01L21/479
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
摘要翻译：一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电材料和至少一种用于通过材料堆的阈值/平带电压调谐的其它装置提供工程。本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。本发明还涉及一种制造这种CMOS结构的方法。

78. 发明申请

US20100320547A1 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC 有权
标题翻译：用于高K栅介质的SCAVANGING金属叠层
公开(公告)号：US20100320547A1
公开(公告)日：2010-12-23
申请号：US12487248
申请日：2009-06-18
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/78 , H01L21/314 , H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

79. 发明授权

US07838908B2 Semiconductor device having dual metal gates and method of manufacture 有权
标题翻译：具有双金属栅极的半导体器件及其制造方法
公开(公告)号：US07838908B2
公开(公告)日：2010-11-23
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L27/10
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

80. 发明授权

US07820552B2 Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack 有权
标题翻译：先进的高k栅极堆叠图案和包含图案化的高k栅极堆叠的结构
公开(公告)号：US07820552B2
公开(公告)日：2010-10-26
申请号：US11685558
申请日：2007-03-13
申请人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
发明人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/31144 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
摘要翻译：提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

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