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71. 发明授权

US07314827B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07314827B2
公开(公告)日：2008-01-01
申请号：US11181908
申请日：2005-07-15
申请人： Hiroshi Toyoda , Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
发明人： Hiroshi Toyoda , Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , C23C14/0635 , C23C14/165
摘要： A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.
摘要翻译：根据本发明的一个方面的制造半导体器件的方法包括在其表面上具有凹陷部分的基板上形成镀膜，以便通过电镀方式将凹陷部分埋入其中; 在电镀膜上形成压缩应力施加膜，该压应力膜由与构成镀膜的金属的热膨胀系数相比具有60％以下的热膨胀系数的材料构成; 通过压应力施加膜向镀膜施加压应力时的热处理; 并且除去未埋设在凹部中的压应力施加膜和镀膜。

72. 发明申请

US20070202699A1 Electronic component fabrication method 审中-公开
标题翻译：电子元件制造方法
公开(公告)号：US20070202699A1
公开(公告)日：2007-08-30
申请号：US11710477
申请日：2007-02-26
申请人： Hiroshi Toyoda , Masahiko Hasunuma
发明人： Hiroshi Toyoda , Masahiko Hasunuma
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , C25D5/34 , C25D7/123 , H01L21/76829 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： A method for fabricating an electronic component, includes forming a seed film above a base body, cooling said seed film, and putting the cooled seed film into a plating solution to perform electro-plating with said seed film being as a cathode.
摘要翻译：一种电子部件的制造方法，其特征在于，在基体的上方形成种子膜，冷却所述种子膜，将所述冷却后的种子膜放入电镀液中进行电镀，所述种子膜为阴极。

73. 发明授权

US07180192B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07180192B2
公开(公告)日：2007-02-20
申请号：US11168928
申请日：2005-06-29
申请人： Masahiko Hasunuma , Sachiyo Ito
发明人： Masahiko Hasunuma , Sachiyo Ito
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L23/3677 , H01L23/522 , H01L23/5283 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material whose Young's modulus is 30 GPa or more, at least one first reinforcing plug which is connected to the conductive layer and which is formed in contact with the reinforcing material, a reinforcing metal layer which is provided in the insulating film in an area other than that where the conductive layer is formed, and which is electrically disconnected from the conductive layer and the conductive plug, and a second reinforcing plug which is connected to the under side of the reinforcing metal layer and which is formed in contact with the reinforcing material.
摘要翻译：半导体器件包括相对介电常数为3.4以下的绝缘膜，至少一个导电层，与导电层电连接以形成导电路径的至少一个导电插塞，至少一种增强材料，其杨氏模量为 30GPa以上的至少一个第一加强塞，其连接到所述导电层并且与所述增强材料接触形成，所述加强金属层设置在所述绝缘膜中的除了所述导电层并且其与导电层和导电插塞电气断开，以及第二加强塞，其连接到加强金属层的下侧，并且与增强材料接触形成。

74. 发明授权

US07119442B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07119442B2
公开(公告)日：2006-10-10
申请号：US10986071
申请日：2004-11-12
申请人： Sachiyo Ito , Masahiko Hasunuma
发明人： Sachiyo Ito , Masahiko Hasunuma
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/74
CPC分类号： H01L21/76835 , H01L21/76807 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a Young's modulus of the first insulating material being 10 GPa or less, a linear expansivity of the first insulating material being greater than 30×10−6° C.−1, and a linear expansivity of the second insulating material being 30×10−6° C.−1 or less, and a second insulating layer formed on the first insulating layer, the second insulating layer having a groove connected to the hole, wherein a linear expansivity α of the first insulating layer within 6 μm from the hole is 30×10−6° C.−1 or less, where α = ∑ i = 1 ⁢ v i ⁢ α i , vi and αi are a volume ratio and a linear expansivity of an i-th insulating material.
摘要翻译：一种半导体器件，包括在半导体衬底上形成的第一绝缘层，并且包括第一绝缘材料，第二绝缘材料和孔，第一绝缘材料的相对介电常数为3以下，第一绝缘材料的杨氏模量材料为10GPa或更小，第一绝缘材料的线性膨胀率大于30×10 -6℃。以及第二绝缘材料的线性膨胀性以及形成在第一绝缘层上的第二绝缘层，第二绝缘层具有连接到孔的凹槽，其中所述第一绝缘层在距离所述孔6μm内的线性膨胀系数α为30×10 -6℃以下，其中 $alpha=Σ我=1{MSUB>}_{/ MO>v，而第i种绝缘材料的体积比和线性膨胀性。}$

75. 发明授权

US07112883B2 Semiconductor device with temperature control mechanism 有权
标题翻译：具有温度控制机构的半导体器件
公开(公告)号：US07112883B2
公开(公告)日：2006-09-26
申请号：US11028664
申请日：2005-01-05
申请人： Masahiko Hasunuma
发明人： Masahiko Hasunuma
IPC分类号： H01L23/485 , H01L23/50 , H01L23/48 , H01L23/66 , H05K1/16
CPC分类号： H01L23/367 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device is provided, the semiconductor device including a semiconductor chip having a first metal heat-conductive medium in the inside thereof, a substrate having a second metal heat-conductive medium thermally connected to the first metal heat-conductive medium, and a temperature control device of which at least a part is disposed on the substrate, thermally connected to the second metal heat-conductive medium, and configured to control the temperature within the semiconductor chip.
摘要翻译：提供一种半导体器件，该半导体器件包括其内部具有第一金属导热介质的半导体芯片，具有与第一金属导热介质热连接的第二金属导热介质的基板，以及温度控制装置，其至少部分设置在所述基板上，热连接到所述第二金属导热介质，并且被配置为控制所述半导体芯片内的温度。

76. 发明授权

US06975033B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06975033B2
公开(公告)日：2005-12-13
申请号：US10247378
申请日：2002-09-20
申请人： Sachiyo Ito , Masahiko Hasunuma , Takashi Kawanoue
发明人： Sachiyo Ito , Masahiko Hasunuma , Takashi Kawanoue
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.
摘要翻译：半导体器件包括其上形成有元件的半导体衬底，形成在半导体衬底上并具有3或更低的相对介电常数的低介电常数绝缘膜，埋入低介电常数绝缘膜中的插塞和布线层以及杨氏模量为15GPa以上的高杨氏模量绝缘膜，并且与低介电常数绝缘膜和插塞之间的插塞侧接触形成。

77. 发明授权

US06552434B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US06552434B2
公开(公告)日：2003-04-22
申请号：US10062468
申请日：2002-02-05
申请人： Masahiko Hasunuma , Hisashi Kaneko , Shohei Shima , Sachiyo Ito
发明人： Masahiko Hasunuma , Hisashi Kaneko , Shohei Shima , Sachiyo Ito
IPC分类号： H01L2348
CPC分类号： H01L21/76847 , H01L21/32051 , H01L21/76814 , H01L21/76826 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

78. 发明授权

US4854978A Manufacturing method for high hardness member 失效
标题翻译：高硬度部件的制造方法
公开(公告)号：US4854978A
公开(公告)日：1989-08-08
申请号：US174910
申请日：1988-03-29
申请人： Kaoru Tada , Masahiko Hasunuma , Mitsuo Kawai
发明人： Kaoru Tada , Masahiko Hasunuma , Mitsuo Kawai
IPC分类号： C21D1/00 , C21D1/06 , C21D1/74 , C21D3/00 , C21D6/00 , C22C38/00 , C22C38/38
CPC分类号： C21D3/00 , C21D6/002 , C21D6/005
摘要： A metal molded shape having a high hardness surface layer which is hard to work is obtained by casting an easy to work alloy member into a desired molded form, and then changing the composition of the member surface by volatilizing off the high vapor pressure elements, carried out by subjecting the easy to work alloy member, to a heat treatment at high temperature.

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