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    • 75. 发明授权
    • Delay circuit
    • 延时电路
    • US07170331B2
    • 2007-01-30
    • US11080685
    • 2005-03-16
    • Toshiyuki ShutokuKoji Hayashi
    • Toshiyuki ShutokuKoji Hayashi
    • H03H11/26
    • H03H11/265H03K5/133H03K2005/00104
    • A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells.Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.
    • 一种延迟电路,包括延迟线以延迟具有串联连接的多个延迟单元的输入信号; PLL电路,为延迟线提供延迟控制电压以控制延迟; 以及选择延迟单元的输出信号之一的第一选择器。 每个延迟单元包括串联连接的两级延迟反相器和连接到第一级的延迟反相器和第二级的延迟反相器的连接点的输出反相器。 第一级的延迟反相器的输入是前一延迟单元中的第二级的延迟反相器的输出信号,第一选择器作为延迟信号输出输出反相器或第二级的延迟反相器的输出信号 在延迟单元之一的阶段。
    • 80. 发明申请
    • Delay circuit
    • 延时电路
    • US20050206425A1
    • 2005-09-22
    • US11080685
    • 2005-03-16
    • Toshiyuki ShutokuKoji Hayashi
    • Toshiyuki ShutokuKoji Hayashi
    • G11B20/10G11B7/00G11B20/14H03H11/26H03K5/00H03K5/14H03L7/00
    • H03H11/265H03K5/133H03K2005/00104
    • A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.
    • 一种延迟电路,包括延迟线以延迟具有串联连接的多个延迟单元的输入信号; PLL电路,为延迟线提供延迟控制电压以控制延迟; 以及选择延迟单元的输出信号之一的第一选择器。 每个延迟单元包括串联连接的两级延迟反相器和连接到第一级的延迟反相器和第二级的延迟反相器的连接点的输出反相器。 第一级的延迟反相器的输入是前一延迟单元中的第二级的延迟反相器的输出信号,第一选择器作为延迟信号输出输出反相器或第二级的延迟反相器的输出信号 在延迟单元之一的阶段。