专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07890731B2 Clearing selected storage translation buffer entries based on table origin address 有权
标题翻译：根据表起始地址清除所选存储转换缓冲区条目
公开(公告)号：US07890731B2
公开(公告)日：2011-02-15
申请号：US11733224
申请日：2007-04-10
申请人： Timothy J. Slegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
发明人： Timothy J. Slegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译：提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。缓冲区条目与段表项或区域表项或ASCE地址相关。该指令可以通过软件仿真，硬件，固件或其组合来实现。

72. 发明授权

US07712076B2 Register indirect access of program floating point registers by millicode 失效
标题翻译：通过millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US07712076B2
公开(公告)日：2010-05-04
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/44
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

73. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

74. 发明申请

US20090182984A1 Execute Relative Long Facility and Instructions Therefore 审中-公开
标题翻译：执行相对较长的设施和说明
公开(公告)号：US20090182984A1
公开(公告)日：2009-07-16
申请号：US11972714
申请日：2008-01-11
申请人： Dan F. Greiner , Timothy J. Slegel , Charles W. Gainey
发明人： Dan F. Greiner , Timothy J. Slegel , Charles W. Gainey
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30167 , G06F9/324 , G06F9/342 , G06F9/355
摘要： A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter to a sign extended immediate field. The fetched target instruction is optionally modified before execution by OR'ing bits into predetermined bits of the target instruction.
摘要翻译：一种用于执行相关指令的方法，系统和程序产品，其在执行时在相对地址处获取并执行目标指令，然后在执行相关指令之后向下一个指令返回处理。通过将程序计数器的值添加到符号扩展的立即数字段来形成相对地址。所获取的目标指令在执行之前可选地被修改以将位对准目标指令的预定位。

75. 发明申请

US20090182981A1 Rotate Then Operate on Selected Bits Facility and Instructions Therefore 有权
标题翻译：旋转然后在所选位设施和说明上操作
公开(公告)号：US20090182981A1
公开(公告)日：2009-07-16
申请号：US11972679
申请日：2008-01-11
申请人： Dan F. Greiner , Timothy J. Slegel , Joachim von Buttlar
发明人： Dan F. Greiner , Timothy J. Slegel , Joachim von Buttlar
IPC分类号： G06F9/315
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/30189 , G06F9/342
摘要： A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
摘要翻译：旋转，然后操作具有T位的指令被执行，其中第一寄存器中的第一操作数旋转一个量，并且对旋转的第一操作数的选定部分执行布尔运算，并且在第二寄存器中执行第二操作数。如果T位为“0”，则将布尔运算结果的选定部分插入到第二寄存器的第二个操作数的相应位中。如果T位为“1”，除了插入的位之外，所转动的第一个操作数的选定部分以外的其他位被保存在第二个寄存器中。

76. 发明申请

US20090182972A1 DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL 有权
标题翻译：动态地址翻译与格式控制
公开(公告)号：US20090182972A1
公开(公告)日：2009-07-16
申请号：US11972697
申请日：2008-01-11
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的索引部分用于引用转换表中的条目。如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。

77. 发明申请

US20090182971A1 DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION 有权
标题翻译：具有保护功能的动态地址转换
公开(公告)号：US20090182971A1
公开(公告)日：2009-07-16
申请号：US11972688
申请日：2008-01-11
申请人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F12/0215 , G06F12/1009 , G06F12/1036 , G06F12/145 , G06F2212/1052 , G06F2212/654 , G06F2212/656 , G06F2212/68
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。基于获得的初始来源，获得段表条目。段表项被配置为包含格式控制和访问有效性字段。如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。

78. 发明申请

US20090182942A1 Extract Cache Attribute Facility and Instruction Therefore 有权
标题翻译：提取缓存属性设备和指令
公开(公告)号：US20090182942A1
公开(公告)日：2009-07-16
申请号：US11972675
申请日：2008-01-11
申请人： Dan F. Greiner , Timothy J. Slegel
发明人： Dan F. Greiner , Timothy J. Slegel
IPC分类号： G06F12/08
CPC分类号： G06F9/30145 , G06F9/30047 , G06F9/30058 , G06F9/30167 , G06F9/322
摘要： A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.
摘要翻译：一种用于指定目标缓存高速缓存级别和感兴趣的目标高速缓存属性的用于获得一个或多个目标高速缓存的高速缓存属性的计算机体系结构的设施和缓存机器指令。所请求的高速缓存属性被保存在一个寄存器中。

79. 发明申请

US20080126759A1 Register Indirect Access of Program Floating Point Registers by Millicode 失效
标题翻译：通过Millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

80. 发明授权

US07082517B2 Superscalar microprocessor having multi-pipe dispatch and execution unit 失效
标题翻译：超标量微处理器具有多管调度和执行单元
公开(公告)号：US07082517B2
公开(公告)日：2006-07-25
申请号：US10435806
申请日：2003-05-12
申请人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
发明人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译：在用作对称多处理器的计算机系统中，超标量微处理器装置允许调度和执行多周期和复杂指令。在调度单元中生成一些控制信号，并且通过指令发送到定点单元（FXU）。多个执行管道对应于指令调度端口，执行单元是包含三个执行数据流管道（X，Y和Z）和一个控制管道（R）的定点单元（FXU）。然后，FXU逻辑在可用的FXU管道上执行这些说明。这导致最佳性能，很少或没有其他并发症。所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式