专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20110031546A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SAME 有权
标题翻译：制造半导体器件的方法及其制造方法
公开(公告)号：US20110031546A1
公开(公告)日：2011-02-10
申请号：US12725662
申请日：2010-03-17
申请人： Tsuneo UENAKA , Kazuyuki Higashi
发明人： Tsuneo UENAKA , Kazuyuki Higashi
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成第一层; 在所述第一层中形成第一接触孔; 在第一个接触孔中埋设牺牲膜; 在第一层和第二接触孔之后形成第二层; 形成在第二层中到达牺牲膜的第二接触孔; 经由所述第二接触孔从所述第一接触孔去除所述牺牲膜; 以及在所述第一接触孔和所述第二接触孔中设置接触电极。

72. 发明申请

US20090091040A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US20090091040A1
公开(公告)日：2009-04-09
申请号：US12199022
申请日：2008-08-27
申请人： Kanae UCHIDA , Masato Endo , Kazuyuki Higashi
发明人： Kanae UCHIDA , Masato Endo , Kazuyuki Higashi
IPC分类号： H01L23/535
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76832 , H01L21/76885 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor storage device includes a memory cell transistor and a selective transistor formed on a semiconductor substrate, a first interlayer insulating film which is formed on the semiconductor substrate, an insulating layer formed by use of a material higher in dielectric constant than the first interlayer insulating film, a contact plug which penetrates the insulating layer and the first interlayer insulating film and which is electrically connected to a drain of the selective transistor, and a bit line which is in contact with the contact plug. A partial region in the bottom surface of the bit line is located lower than the upper surface of the contact plug, and is in contact with the surface of the insulating layer, and the partial region is also in contact with the side surface of the contact plug.
摘要翻译：半导体存储装置包括存储单元晶体管和形成在半导体衬底上的选择晶体管，形成在半导体衬底上的第一层间绝缘膜，使用介电常数高于第一层间绝缘体的材料形成的绝缘层薄膜，穿过绝缘层和第一层间绝缘膜并且与导体连接到选择晶体管的漏极的接触插塞和与接触插头接触的位线。位线底面的部分区域位于比接触插塞的上表面低的位置，与绝缘层的表面接触，部分区域也与接点的侧面接触插头。

73. 发明授权

US07084510B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07084510B2
公开(公告)日：2006-08-01
申请号：US10765833
申请日：2004-01-29
申请人： Kazuyuki Higashi , Noriaki Matsunaga
发明人： Kazuyuki Higashi , Noriaki Matsunaga
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76874 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has an active element structure formed on a semiconductor substrate. A first insulating film is provided above the semiconductor substrate. A first interconnect layer composed of copper is provided in a surface of the first insulating film. A second insulating film is provided on the first insulating film. A connection hole is formed in the second insulating film and has its bottom connected to the first insulating layer. A connection plug composed of a single crystal of copper is filled in the connection hole so that no other crystals of copper are provided in the connection hole. An interconnect trench is formed in a surface of the second insulating film and has its bottom connected to the connection hole. A second interconnect layer is provided in the interconnect trench.
摘要翻译：半导体器件具有形成在半导体衬底上的有源元件结构。第一绝缘膜设置在半导体衬底的上方。由铜构成的第一互连层设置在第一绝缘膜的表面上。在第一绝缘膜上设置第二绝缘膜。连接孔形成在第二绝缘膜中，并且其底部连接到第一绝缘层。在连接孔中填充由铜单晶组成的连接插头，使得连接孔中不设置其他的铜晶体。互连沟槽形成在第二绝缘膜的表面中，并且其底部连接到连接孔。第二互连层设置在互连沟槽中。

74. 发明申请

US20060121734A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060121734A1
公开(公告)日：2006-06-08
申请号：US11095567
申请日：2005-04-01
申请人： Kazuyuki Higashi , Masaki Yamada , Noriaki Matsunaga
发明人： Kazuyuki Higashi , Masaki Yamada , Noriaki Matsunaga
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , Y10S438/927
摘要： A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.
摘要翻译：根据本发明实施例的形成有多层互连结构的半导体集成电路的半导体器件包括在铜布线的上表面上形成的铜布线和绝缘层，其中铜布线包括用于改善铜布线和绝缘层之间的粘附性的添加剂，并且添加剂的轮廓具有随着从铜布线的顶表面朝向其内部逐渐减小浓度的梯度，并且具有在铜线上表面最高的浓度。

75. 发明申请

US20060097399A1 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product 失效
标题翻译：产生图案的方法，制造半导体器件的方法，半导体器件和计算机程序产品
公开(公告)号：US20060097399A1
公开(公告)日：2006-05-11
申请号：US11265231
申请日：2005-11-03
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： H01L23/48
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

76. 发明申请

US20050206438A1 Drive circuit for voltage driven type semiconductor element 有权
标题翻译：用于电压驱动型半导体元件的驱动电路
公开(公告)号：US20050206438A1
公开(公告)日：2005-09-22
申请号：US11077208
申请日：2005-03-11
申请人： Kazuyuki Higashi
发明人： Kazuyuki Higashi
IPC分类号： H02M1/00 , H03K17/16 , H03K17/56 , H02P3/10
CPC分类号： H03K17/166 , H03K17/0828
摘要： A drive circuit for a voltage driven type semiconductor element, includes: an electrical charge discharge unit that discharges electrical charge from a gate terminal of a voltage driven type semiconductor element when the voltage driven type semiconductor element is turned OFF; and an electrical discharge control unit that detects a time variation of a collector voltage of the voltage driven type semiconductor element, and controls electric discharge by the electrical charge discharge unit according to the time variation of the collector voltage which has been detected.
摘要翻译：一种用于电压驱动型半导体元件的驱动电路，包括：电压放电单元，当电压驱动型半导体元件断开时，从电压驱动型半导体元件的栅极端子排出电荷; 以及放电控制单元，其检测所述电压驱动型半导体元件的集电极电压的时间变化，并且根据所检测的集电极电压的时间变化来控制所述电荷放电单元的放电。

77. 发明授权

US06946221B2 Square battery container, method of manufacturing the container, and square battery using the container 失效
标题翻译：方形电池容器，容器的制造方法以及使用容器的方形电池
公开(公告)号：US06946221B2
公开(公告)日：2005-09-20
申请号：US10181634
申请日：2001-12-26
申请人： Tomomichi Ueda , Susumu Kitaoka , Katsuhiko Mori , Shoji Yamashita , Kazuyuki Higashi , Tadahiro Tokumoto , Masatoshi Hano
发明人： Tomomichi Ueda , Susumu Kitaoka , Katsuhiko Mori , Shoji Yamashita , Kazuyuki Higashi , Tadahiro Tokumoto , Masatoshi Hano
IPC分类号： H01M2/02 , H01M2/08 , H01M6/10 , H01M10/052 , B21D22/00 , B21D22/20
CPC分类号： H01M2/0285 , H01M2/0202 , H01M2/0217 , H01M2/08 , H01M10/052 , H01M2006/106
摘要： A prismatic battery case with high dimensional precision is manufactured, while pursuing an improvement in productivity, with a manufacturing method of a prismatic battery case that includes a first step for molding an intermediate cup body (8) by impact molding a pellet (7) of prescribed shape, and a second step for molding a prismatic battery case (9) with a cross section of substantially rectangular shape by DI processing the intermediate cup body (8). The DI processing conducts drawing and ironing continuously, in one action.
摘要翻译：制造具有高尺寸精度的棱柱形电池壳体，同时追求生产率的提高，其中制造方法为棱柱形电池盒，该方法包括：通过冲击成型中间杯体（8）的第一步骤，以及通过DI加工中间杯体（8）成型具有大致矩形截面的棱柱形电池壳体（9）的第二步骤。 DI处理在一个动作中连续进行绘图和熨烫。

78. 发明申请

US20050029985A1 Battery can, and battery using the battery can 审中-公开
标题翻译：电池可以和电池使用电池
公开(公告)号：US20050029985A1
公开(公告)日：2005-02-10
申请号：US10492064
申请日：2002-10-11
申请人： Masatoshi Hano , Kazuyuki Higashi , Tadahiro Tokumoto
发明人： Masatoshi Hano , Kazuyuki Higashi , Tadahiro Tokumoto
IPC分类号： H01M2/02 , H02J7/00
CPC分类号： H01M2/0207 , H01M2/0217 , H01M10/052
摘要： Battery case for containing electrode assembly and electrolyte of electroltic battery has a grid on at least a portion of an inner surface of the case, formed by intersecting pluralities of first and second ridges. The grid enables construction of a battery case of minimal thickness while having high strength and rigidity, and resistance to deformation caused by generation of higher internal battery pressure during use.
摘要翻译：用于包含电极组件和电解电池的电解质的电池壳体在壳体的内表面的至少一部分上具有由多个第一和第二脊部相交形成的网格。电网可以实现最小厚度的电池壳体的构造，同时具有高强度和刚性，并且在使用期间由于产生更高的内部电池压力而导致的变形阻力。

79. 发明申请

US20050023701A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050023701A1
公开(公告)日：2005-02-03
申请号：US10706043
申请日：2003-11-13
申请人： Akihiro Kajita , Kazuyuki Higashi
发明人： Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L23/522 , H01L21/768 , H01L23/485 , H01L23/532 , H01L23/48 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the semiconductor substrate to the connection region. A contact plug is provided in the contact hole. A clearance formed in the contact plug is formed with a buried conductive film consisting of a material different from the contact plug. The buried conductive film has a continuous surface without forming a step with the surface of the contact plug.
摘要翻译：半导体器件包括形成在半导体衬底上并具有形成在半导体衬底的表面中的连接区域的有源元件结构。接触孔从形成在半导体衬底上的第一绝缘膜的表面延伸到连接区域。在接触孔中设置接触塞。在接触插塞中形成的间隙形成有由与接触插塞不同的材料构成的掩埋导电膜。掩埋导电膜具有连续表面，而不形成与接触插塞表面的台阶。

80. 发明授权

US06803300B2 Method of manufacturing a semiconductor device having a ground plane 有权
标题翻译：制造具有接地面的半导体器件的方法
公开(公告)号：US06803300B2
公开(公告)日：2004-10-12
申请号：US10314995
申请日：2002-12-10
申请人： Kazuyuki Higashi , Noriaki Matsunaga
发明人： Kazuyuki Higashi , Noriaki Matsunaga
IPC分类号： H01L2144
CPC分类号： H01L23/53252 , H01L21/76834 , H01L21/76849 , H01L23/5222 , H01L23/53223 , H01L23/53228 , H01L23/53242 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.
摘要翻译：半导体器件至少包括设置在半导体衬底上的绝缘体的表面上的第一和第二下层布线，设置在绝缘体上以覆盖第一和第二下层布线的表面的第一层间膜，第一和第二连接布线，设置在第一层间膜上，并且包括分别与第一和第二下层布线接触的第一和第二膜，以及连续设置在第二连接布线上并且至少包括第一膜的平板电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式