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71. 发明申请

US20150253385A1 Isometric Test Compression With Low Toggling Activity 有权
标题翻译：具有低切换活动的等轴测试压缩
公开(公告)号：US20150253385A1
公开(公告)日：2015-09-10
申请号：US14642501
申请日：2015-03-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Amit Kumar , Mark A. Kassab , Elham Moghaddam , Nilanjan Mukherjee , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/3177
CPC分类号： G01R31/318342 , G01R31/318547 , G01R31/318583
摘要： Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.
摘要翻译：所公开技术的各个方面涉及创建用于测试模式生成的测试模板的技术。首先基于电路设计的信号概率分析生成多个故障的残余测试立方体。然后基于合并剩余测试立方体生成测试模板。最后，基于测试模板之一生成多个测试图案和/或压缩测试立方体。

72. 发明授权

US09003248B2 Fault-driven scan chain configuration for test-per-clock 有权
标题翻译：故障驱动的扫描链配置用于每个时钟测试
公开(公告)号：US09003248B2
公开(公告)日：2015-04-07
申请号：US13919998
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318575
摘要： Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.
摘要翻译：本发明的方面涉及使用故障驱动技术来产生用于每个时钟测试的扫描链配置。首先生成检测多个故障的多个测试立方体。然后将用于加载测试立方体的指定位的扫描链分配给刺激组。从多个测试立方体中，选择检测大量不排斥到刺激组中的扫描链的故障的测试立方体。一个或多个不在刺激组中并且用于观察大量故障所需的扫描链被分配给压实组。压实组中或在压实组和刺激组中的扫描链的数量可以被限制为预定数量。

73. 发明授权

US08996941B2 Test data volume reduction based on test cube properties 有权
标题翻译：基于测试立方体属性测试数据量减少
公开(公告)号：US08996941B2
公开(公告)日：2015-03-31
申请号：US13914529
申请日：2013-06-10
申请人： Mentor Graphics Corporation
发明人： Xijiang Lin , Janusz Rajski
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318544 , G01R31/318547
摘要： Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.
摘要翻译：基于用于测试电路产生的多个测试立方体的指定位分布信息，从电路中的扫描单元中选择背景扫描单元。然后，对于多个测试立方体中的每个测试立方体，确定主要部分和背景部分。背景部分对应于背景扫描单元。在具有兼容的主要部分的多个测试立方体中测试立方体被合并到测试立方体组中。测试多维数据集中的每个测试立方体组都包含主测试立方体和后台测试立方体。由测试器或解压缩器提供的主要测试立方体可以被移动到扫描链中。背景测试立方体可以被转移到背景链中，并且基于控制信号插入到扫描链中的主测试立方体中。

74. 发明申请

US20140372824A1 Test Generation For Test-Per-Clock 有权
标题翻译：用于每个时钟测试的测试生成
公开(公告)号：US20140372824A1
公开(公告)日：2014-12-18
申请号：US13919984
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3183
CPC分类号： G01R31/318307 , G01R31/318544 , G01R31/318563
摘要： Aspects of the invention relate to test generation techniques for test-per-clock. Test cubes may be generated by adding constraints to a conventional automatic test pattern generator. During a test cube merging process, a first test cube is merged with one or more test cubes that are compatible with the first test cube to generate a second test cube. The second test cube is shifted by one bit along a direction of scan chain shifting to generate a third test cube. The third test cube is then merged with one or more test cubes in the test cubes that are compatible with the third test cube to generate a fourth test cube. The shifting and merging operations may be repeated for a predetermined number of times.
摘要翻译：本发明的方面涉及用于每个时钟测试的测试生成技术。可以通过向传统的自动测试图案发生器添加约束来生成测试立方体。在测试多维数据集合并过程中，第一个测试多维数据集与一个或多个与第一个测试多维数据集兼容的测试多维数据集合并生成第二个测试多维数据集。第二个测试立方体沿着扫描链转换的方向移位一位，以产生第三个测试立方体。然后，第三个测试多维数据集与测试多维数据集中的一个或多个与第三个测试多维数据集兼容的测试立方体合并，以生成第四个测试多维数据集。移动和合并操作可以重复预定次数。

75. 发明申请

US20140372818A1 Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains 有权
标题翻译：基于动态分区可重构扫描链的每个时钟测试
公开(公告)号：US20140372818A1
公开(公告)日：2014-12-18
申请号：US13919974
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3177
CPC分类号： G01R31/318555 , G01R31/31704 , G01R31/3177 , G01R31/318544 , G01R31/318547 , G01R31/318575
摘要： Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
摘要翻译：本发明的方面涉及基于动态分配的可重构扫描链的基于每时钟的测试方案。每个时钟周期，由控制信号配置的扫描链在移位启动模式下运行，测试刺激一位移位，并立即将新形成的测试模式应用于待测电路; 以及由控制信号配置的扫描链，以捕捉 - 压缩 - 移位模式运行，移除先前压缩的一个测试响应数据，同时用当前捕获的测试响应压缩先前压缩的测试响应数据的剩余位，以形成当前压缩测试响应数据。可以通过控制信号来配置大量扫描链，以在任务模式下工作。在预定数量的时钟周期之后，可以应用不同的控制信号来重新配置和划分扫描链以施加不同的测试刺激。

76. 发明申请

US20140223247A1 SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS 有权
标题翻译：用于堆叠设计中的互连的基于扫描的测试架构
公开(公告)号：US20140223247A1
公开(公告)日：2014-08-07
申请号：US14170804
申请日：2014-02-03
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/3177
CPC分类号： G01R31/318563 , G01R31/318513
摘要： Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.
摘要翻译：本发明的方面涉及堆叠设计中的互连的基于扫描的测试架构。所公开的基于扫描的测试架构包括扫描链。扫描链上的扫描单元被配置为基于控制信号的位来接收来自相邻扫描单元的输出或将来自硅通孔的数据与来自相邻扫描单元的输出的数据组合的混合设备的输出的数据。基于扫描的测试架构可用于识别单个或多个有缺陷的硅通孔。

77. 发明申请

US20140006888A1 CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES 有权
标题翻译：测试模式的连续应用和分解以及测试响应的选择性压缩
公开(公告)号：US20140006888A1
公开(公告)日：2014-01-02
申请号：US14021800
申请日：2013-09-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

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