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71. 发明申请

US20090212341A1 SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体金属氧化物半导体场效应晶体管
公开(公告)号：US20090212341A1
公开(公告)日：2009-08-27
申请号：US12034899
申请日：2008-02-21
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译：在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

72. 发明申请

US20090129485A1 Structure for transmitter bandwidth optimization circuit 有权
标题翻译：发射机带宽优化电路的结构
公开(公告)号：US20090129485A1
公开(公告)日：2009-05-21
申请号：US11985963
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, JR. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, JR. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
IPC分类号： H04B3/00 , H04L27/00
CPC分类号： H04L25/0286 , H04L25/03343
摘要： A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构提供具有根据操作参数可控的频率响应的发射机，并且可以包括可操作地存储用于控制每个发射机的频率响应的操作参数的存储器的多个相应的操作条件。可以使用传感器来检测操作状态。响应于检测到的操作条件的变化，可以使用与检测到的操作条件对应的存储的操作参数来控制发送器的频率响应。

73. 发明申请

US20080316930A1 Robust Cable Connectivity Test Receiver For High-Speed Data Receiver 有权
标题翻译：用于高速数据接收器的坚固的电缆连接测试接收器
公开(公告)号：US20080316930A1
公开(公告)日：2008-12-25
申请号：US11766268
申请日：2007-06-21
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： G01R31/08
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译：提供了一种用于检测信号传输路径中的故障的系统。在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低的信号电压衰减摇摆。期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。

74. 发明申请

US20080266984A1 Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection 有权
标题翻译：用于加速DRAM软错误检测的可编程重离子感测装置
公开(公告)号：US20080266984A1
公开(公告)日：2008-10-30
申请号：US12134347
申请日：2008-06-06
申请人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H.K. Tang
发明人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H.K. Tang
IPC分类号： G11C7/10
CPC分类号： G11C11/406 , G01R31/31816 , G11C11/401 , G11C11/40615 , G11C11/4078 , G11C11/4091 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/52 , G11C2029/5002
摘要： Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
摘要翻译：本发明的方面涉及用于加速DRAM软错误检测的可编程重离子感测装置。优选将基于DRAM的α粒子感测装置的设计用作加速片上SER测试车辆。该感测装置具有可编程的感应余量，刷新率和电源电压，以达到SER灵敏度的各种程度。另外，提出了双模DRAM阵列，使得阵列的至少一部分可以用于在软错误检测（SED）模式期间监视高能量粒子活动。

75. 发明授权

US07442579B2 Methods to achieve precision alignment for wafer scale packages 失效
标题翻译：实现晶圆级封装精密对准的方法
公开(公告)号：US07442579B2
公开(公告)日：2008-10-28
申请号：US10994574
申请日：2004-11-22
申请人： Howard Hao Chen , Louis L. Hsu
发明人： Howard Hao Chen , Louis L. Hsu
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L21/52 , H01L24/83 , H01L2223/5448 , H01L2223/54486 , H01L2924/1461 , H01L2924/00
摘要： Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.
摘要翻译：用于制造集成晶片级封装的方法，其减小载体衬底的芯片和凹坑之间的潜在的未对准。根据本发明的一个方面，一种制造半导体器件的方法包括：设置在载体衬底上的光致抗蚀剂层，放置在光致抗蚀剂层的表面上的芯片。使用芯片作为掩模对光致抗蚀剂层进行图案化。在图案化步骤之后，将芯片从光致抗蚀剂层上除去。在载体基板上形成有袋状物，将被除去的芯片放置在形成于载体基板上的槽内。

76. 发明申请

US20080137721A1 Automatic adaptive equalization method for high-speed serial transmission link 失效
标题翻译：自动自适应均衡方法用于高速串行传输链路
公开(公告)号：US20080137721A1
公开(公告)日：2008-06-12
申请号：US11974967
申请日：2007-10-17
申请人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Huihao Xu
发明人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Huihao Xu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03343
摘要： In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.
摘要翻译：在用于执行通信系统的均衡的方法中，可以将预定信号从发射机单元发送到传输线上的下行信道方向上的接收机单元，例如作为在相应方向上同时沿相反方向转变的一对差分信号传输线的信号导体。在接收机单元，可以分析从传输线接收的信号的眼图，以确定均衡信息。均衡信息可以在传输线上的上行方向上从接收机单元发送到发射机单元，并在发射机单元处接收。使用接收到的均衡信息，可以调整发送单元的发送特性。

77. 发明授权

US07145413B2 Programmable impedance matching circuit and method 失效
标题翻译：可编程阻抗匹配电路及方法
公开(公告)号：US07145413B2
公开(公告)日：2006-12-05
申请号：US10250177
申请日：2003-06-10
申请人： Louis L. Hsu , Joseph Natonio , Daniel W. Storaska , William F. Washburn
发明人： Louis L. Hsu , Joseph Natonio , Daniel W. Storaska , William F. Washburn
IPC分类号： H03H7/38
CPC分类号： H03H7/38
摘要： As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.
摘要翻译：如本文所公开的，提供微电子电路和方法来改善传输线处的信号完整性。该电路包括可编程调节的阻抗匹配电路，其耦合到包括可编程调节的电感元件的传输线。可编程可调节阻抗匹配电路理想地设置在与传输线耦合的接收器或发射器相同的芯片上，或者替代地在与包括接收器或发射器的芯片一起封装的元件上。可编程可调阻抗匹配电路的阻抗可以响应于控制输入而调节，以改善传输线处的信号完整性。

78. 发明授权

US07092235B2 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US07092235B2
公开(公告)日：2006-08-15
申请号：US11043760
申请日：2005-01-26
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/06
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。多个导电层被一层电介质材料隔开。电容器的电介质材料暴露于离子束。离子束包括至少一种材料的离子，以改变介电材料的介电常数。

79. 发明授权

US07041552B2 Integrated metal-insulator-metal capacitor and metal gate transistor 失效
标题翻译：集成金属 - 绝缘体 - 金属电容器和金属栅极晶体管
公开(公告)号：US07041552B2
公开(公告)日：2006-05-09
申请号：US10787487
申请日：2004-02-26
申请人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
IPC分类号： H01L21/8242
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/28114 , H01L27/0629 , H01L27/10805 , H01L27/1085 , H01L27/10885 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.
摘要翻译：公开了一种集成电路结构，其包括一对电容器，每个电容器具有由绝缘体分隔的金属板和与电容器电连接的金属栅极半导体晶体管。晶体管的金属栅极和每个电容器的金属板之一在集成电路结构中包括相同的金属电平。更具体地，每个电容器包括垂直电容器，其具有垂直于下金属板上的上金属板，并且晶体管的每个金属栅极和电容器的每个上金属板在集成电路结构中包括相同的金属电平。

80. 发明授权

US07038319B2 Apparatus and method to reduce signal cross-talk 失效
标题翻译：降低信号串扰的装置和方法
公开(公告)号：US07038319B2
公开(公告)日：2006-05-02
申请号：US10644372
申请日：2003-08-20
申请人： Patrick H. Buffet , Charles S. Chiu , Jon D. Garlett , Louis L. Hsu , Brian J. Schuh
发明人： Patrick H. Buffet , Charles S. Chiu , Jon D. Garlett , Louis L. Hsu , Brian J. Schuh
IPC分类号： H01L23/48
CPC分类号： H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
摘要翻译：公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。用于承载第一信号的第一对导体提供在载体的层中。用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化，而不会增加包装的尺寸。第一对导体的高度比第二对导体短。或者，第一和第二对导体被配置成使得它们彼此均匀地影响。芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

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