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71. 发明申请

US20060284250A1 Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
公开(公告)号：US20060284250A1
公开(公告)日：2006-12-21
申请号：US11154906
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

72. 发明申请

US20060151851A1 ON-PAD BROADBAND MATCHING NETWORK 失效
标题翻译： ON-PAD宽带配对网络
公开(公告)号：US20060151851A1
公开(公告)日：2006-07-13
申请号：US10905624
申请日：2005-01-13
申请人： Edward Pillai , Louis Hsu , Wolfgang Sauter , Daniel Storaska
发明人： Edward Pillai , Louis Hsu , Wolfgang Sauter , Daniel Storaska
IPC分类号： H01L23/48
CPC分类号： H01L23/5227 , H01L23/66 , H01L24/05 , H01L24/48 , H01L27/0255 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/131 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00011 , H01L2224/45099 , H01L2924/00
摘要： A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.
摘要翻译：提供了芯片，其中片上匹配网络具有导电连接到芯片的焊盘的第一端子和导电连接到芯片上的公共节点的第二端子。接线迹线将片上匹配网络连接到芯片的电路。片上匹配网络包括具有至少一个二极管的静电放电保护（ESD）电路，其具有导电连接到接合焊盘的第一端子和连接到固定电位源的过电压放电路径的第二端子。匹配网络还包括耦合以在接合焊盘和布线迹线之间提供第一感应路径的第一电感器，具有连接到公共节点的第一端子的终端电阻器，以及耦合以在第二电感器之间提供第二电感路径的第二电感器接线迹线和终端电阻的第二个端子。

73. 发明申请

US20060110852A1 Methods to achieve precision alignment for wafer scale packages 失效
标题翻译：实现晶圆级封装精密对准的方法
公开(公告)号：US20060110852A1
公开(公告)日：2006-05-25
申请号：US10994574
申请日：2004-11-22
申请人： Howard Chen , Louis Hsu
发明人： Howard Chen , Louis Hsu
IPC分类号： H01L21/48
CPC分类号： H01L23/5389 , H01L21/52 , H01L24/83 , H01L2223/5448 , H01L2223/54486 , H01L2924/1461 , H01L2924/00
摘要： Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.
摘要翻译：用于制造集成晶片级封装的方法，其减小载体衬底的芯片和凹坑之间的潜在的未对准。根据本发明的一个方面，一种制造半导体器件的方法包括：设置在载体衬底上的光致抗蚀剂层，放置在光致抗蚀剂层的表面上的芯片。使用芯片作为掩模对光致抗蚀剂层进行图案化。在图案化步骤之后，将芯片从光致抗蚀剂层上除去。在载体基板上形成有袋状物，将被除去的芯片放置在形成于载体基板上的槽内。

74. 发明申请

US20060067440A1 High Speed Multi-Mode Receiver 有权
标题翻译：高速多模式接收机
公开(公告)号：US20060067440A1
公开(公告)日：2006-03-30
申请号：US10711713
申请日：2004-09-30
申请人： Louis Hsu , Brian Ji , James Mason , Karl Selander , Michael Sorna , Steven Zier
发明人： Louis Hsu , Brian Ji , James Mason , Karl Selander , Michael Sorna , Steven Zier
IPC分类号： H03K5/01 , H04B1/10 , H04L25/08
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译：提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

75. 发明申请

US20050282323A1 Hybrid substrate and method for fabricating the same 失效
标题翻译：混合基板及其制造方法
公开(公告)号：US20050282323A1
公开(公告)日：2005-12-22
申请号：US11202834
申请日：2005-08-12
申请人： Louis Hsu , Li-Kong Wang
发明人： Louis Hsu , Li-Kong Wang
IPC分类号： H01L21/20 , H01L27/12 , D06N7/04 , G11B5/64 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/12 , H01L21/02381 , H01L21/0243 , H01L21/02527 , Y10T428/12674 , Y10T428/24355 , Y10T428/24802 , Y10T428/24942 , Y10T428/30
摘要： A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.
摘要翻译：提出了混合基板，即由不同材料制造的基板及其制造方法。混合基板被配置为在其上制造两个以上的不同器件，具有高导热性，并且被配置用于在其上构图互连以互连在混合基板上制造的不同器件。

76. 发明申请

US20050281343A1 AUTOMATIC ADAPTIVE EQUALIZATION METHOD AND SYSTEM FOR HIGH-SPEED SERIAL TRANSMISSION LINK 失效
标题翻译：用于高速串行传输链路的自动适应均衡方法和系统
公开(公告)号：US20050281343A1
公开(公告)日：2005-12-22
申请号：US10710064
申请日：2004-06-16
申请人： Louis Hsu , Karl Selander , Michael Sorna , Jeremy Stephens , Huihao Xu
发明人： Louis Hsu , Karl Selander , Michael Sorna , Jeremy Stephens , Huihao Xu
IPC分类号： H04L25/00 , H04L25/03
CPC分类号： H04L25/03057 , H04L25/03343
摘要： A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.
摘要翻译：数据通信系统包括发射机单元和接收机单元。发送单元具有根据均衡信息可调的传输特性。发送单元可操作以发送预定信号，并且接收器单元可操作以接收预定信号。接收机单元进一步可操作以通过检查接收到的信号的眼图来产生均衡信息，并将均衡信息发送到发射机单元。

77. 发明申请

US20050275977A1 Multi-level power supply system for a complementary metal oxide semiconductor circuit 有权
标题翻译：用于互补金属氧化物半导体电路的多电平供电系统
公开(公告)号：US20050275977A1
公开(公告)日：2005-12-15
申请号：US10867094
申请日：2004-06-14
申请人： Rajiv Joshi , Louis Hsu
发明人： Rajiv Joshi , Louis Hsu
IPC分类号： G06F1/26 , G11C5/14 , G11C11/4074 , H02H7/00
CPC分类号： G11C11/4074 , G06F1/26 , G11C5/14 , Y10T307/305
摘要： There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2
摘要翻译：提供了一种用于管理多电平电源的方法。该方法包括将较低电压电源总线的电压电平（Vs 1）与较高电压电源总线的电压电平（Vs 2）进行比较，以及如果Vs 2将电流从低电压电源总线路由到较高电压电源总线

78. 发明申请

US20050127978A1 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US20050127978A1
公开(公告)日：2005-06-16
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H01C17/22 , H03K3/00
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

79. 发明申请

US20050059238A1 Cooling system for a semiconductor device and method of fabricating same 有权
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20050059238A1
公开(公告)日：2005-03-17
申请号：US10661299
申请日：2003-09-12
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H01L21/44 , H01L21/48 , H01L23/367
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

80. 发明申请

US20050040536A1 Apparatus and method to reduce signal cross-talk 失效
标题翻译：降低信号串扰的装置和方法
公开(公告)号：US20050040536A1
公开(公告)日：2005-02-24
申请号：US10644372
申请日：2003-08-20
申请人： Patrick Buffet , Charles Chiu , Jon Garlett , Louis Hsu , Brian Schuh
发明人： Patrick Buffet , Charles Chiu , Jon Garlett , Louis Hsu , Brian Schuh
IPC分类号： H01L23/12 , H01L23/64 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
摘要翻译：公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。用于承载第一信号的第一对导体提供在载体的层中。用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化，而不增加包装的尺寸。第一对导体的高度比第二对导体短。或者，第一和第二对导体被配置成使得它们彼此均匀地影响。芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

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