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71. 发明授权

US06790702B2 Three-dimensional multichip module 失效
标题翻译：三维多芯片模块
公开(公告)号：US06790702B2
公开(公告)日：2004-09-14
申请号：US10178183
申请日：2002-06-21
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L23/4822 , H01L24/01 , H01L25/065 , H01L25/18 , H01L2224/32145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2924/14 , H01L2924/00
摘要： A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chips, A to D converter chips, and other chips in a compact package. The module permits chips that require extensive cooling to be positioned within the structure in a manner such that a large surface area of the chip is not in contact with other chips. The module also permits extensive interconnection between chips within the module.
摘要翻译：一种三维多芯片模块，其具有由堆叠中固定在一起的多个芯片形成的基部结构以及安装到基部结构的外表面的多个外部芯片。多芯片模块可以以紧凑的封装结合存储器芯片，处理器芯片，逻辑芯片，A到D转换器芯片和其他芯片。模块允许需要大量冷却的芯片以这样的方式定位在结构内，使得芯片的大表面积不与其它芯片接触。该模块还允许在模块内的芯片之间进行广泛的互连。

72. 发明授权

US06784550B2 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication 有权
标题翻译：用于在集成电路制造中改进的CMP工艺的金属合金的热处理
公开(公告)号：US06784550B2
公开(公告)日：2004-08-31
申请号：US09945536
申请日：2001-08-30
申请人： Paul A. Farrar , John H. Givens
发明人： Paul A. Farrar , John H. Givens
IPC分类号： H01L2349
CPC分类号： H01L23/53219 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.
摘要翻译：描述了一种热处理方法，其改进集成电路金属抛光并增加抛光后的导电性。描述了一种在集成电路中制造金属层的方法，其包括以下步骤：沉积包含合金掺杂剂沉淀物的金属合金层，以及执行集成电路的第一退火以将合金掺杂剂驱动为固溶体。在用抛光工艺除去多余的金属合金之前，将金属淬火以防止合金掺杂剂从溶液中脱出。为了提高抛光后的导电性，允许掺杂剂从溶液中脱出。金属合金被描述为具有硅和铜的合金掺杂剂的铝，其中在400-500℃下进行第一次退火。该工艺特别适用于使用双镶嵌工艺形成的互连的制造。集成电路被描述为任何电路，但是可以是诸如DRAM的存储器件。

73. 发明授权

US06780721B2 Low dielectric constant shallow trench isolation 有权
公开(公告)号：US06780721B2
公开(公告)日：2004-08-24
申请号：US10435171
申请日：2003-05-08
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

74. 发明授权

US06686654B2 Multiple chip stack structure and cooling system 有权
标题翻译：多芯片堆叠结构和冷却系统
公开(公告)号：US06686654B2
公开(公告)日：2004-02-03
申请号：US09945042
申请日：2001-08-31
申请人： Paul A. Farrar , Jerome M. Eldridge
发明人： Paul A. Farrar , Jerome M. Eldridge
IPC分类号： H01L2302
CPC分类号： H01L25/0652 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： An electronic package comprised of multiple chip stacks attached together to form a single, compact electronic module. The module is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A structure that allows for densely-packed, multiple chip stack electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic packages.
摘要翻译：由多个芯片堆叠组成的电子封装件，其连接在一起以形成单个紧凑的电子模块。模块密封在外壳中。外壳包括加压的导热流体，其用于冷却封闭芯片堆叠。允许制造密集堆叠的多芯片堆叠电子封装的结构，其具有改善的散热效率，从而提高多芯片电子封装的性能和可靠性。

75. 发明授权

US06649522B2 Etch stop in damascene interconnect structure and method of making 有权
公开(公告)号：US06649522B2
公开(公告)日：2003-11-18
申请号：US10245508
申请日：2002-09-18
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2144
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5226 , H01L23/53223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.

76. 发明授权

US06620638B1 Testing of multi-chip electronic modules 失效
标题翻译：多芯片电子模块测试
公开(公告)号：US06620638B1
公开(公告)日：2003-09-16
申请号：US10163402
申请日：2002-06-05
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2166
CPC分类号： H01L21/6835 , H01L22/22 , H01L2924/0002 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： An in-process test sequence for integrated circuit chips that can be used to provide more accurate test results when the integrated circuit device properties are temporarily altered during the fabrication process. The test sequence comprises special Kerf tests for device property and metallurgy, slow speed tests to determine device and chip connectivity, and a final high performance test after the module is assembled. Device properties are tested via special Kerf sites before formation of a temporary material that may increase the capacitive load of the circuits and adversely impact the device properties. The in-process slow speed tests are designed to test the chips and devices at a speed substantially slower than their rated speeds so as to reduce the impact of the increase in capacitive load brought about by the temporary support material. After the module is assembled and temporary material removed, the module is exercised at its rated speed in a high final performance test. The yield of the final test should be relatively high as the various characteristics of the chips have already been screened in a piecemeal manner throughout the fabrication process.
摘要翻译：集成电路芯片的过程中测试序列，可用于在制造过程中临时改变集成电路器件特性时提供更准确的测试结果。测试顺序包括用于器件属性和冶金的特殊Kerf测试，用于确定器件和芯片连接的慢速测试，以及模块组装后的最终高性能测试。在形成可能增加电路的电容性负载并不利地影响器件性能的临时材料之前，通过特殊的Kerf位点测试器件属性。过程中的慢速测试旨在以比其额定速度快得多的速度测试芯片和设备，以便减少由临时支撑材料带来的容性负载增加的影响。模块组装完成后，拆下临时材料后，模块在额定转速下进行高性能测试。最终测试的产量应该相对较高，因为芯片的各种特性已经在整个制造过程中以零碎的方式进行了筛选。

77. 发明授权

US06522011B1 Low capacitance wiring layout and method for making same 有权
公开(公告)号：US06522011B1
公开(公告)日：2003-02-18
申请号：US09638390
申请日：2000-08-15
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L23/5222 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

78. 发明授权

US06510080B1 Three terminal magnetic random access memory 有权
公开(公告)号：US06510080B1
公开(公告)日：2003-01-21
申请号：US09940976
申请日：2001-08-28
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： G11C1114
CPC分类号： G11C11/16
摘要： Three terminal magnetic random access memory structures and methods. One aspect is a memory cell. One embodiment of the memory cell includes a first conductor line, a second conductor line, a third conductor line, and a magnetic storage element. The magnetic storage element is operably positioned to be magnetically coupled to first, second and third magnetic fields produced by energized first, second and third conductor lines, respectively. The magnetic storage element is adapted to be written by a vector sum of the first, second and third magnetic fields. One aspect is a method for writing to a magnetic storage device. According to one embodiment of this method, first, second and third magnetic field vectors are formed at the magnetic storage device. The magnetic storage device is written by a vector sum of the first, second and third magnetic field vectors.

79. 发明授权

US06509590B1 Aluminum-beryllium alloys for air bridges 失效
公开(公告)号：US06509590B1
公开(公告)日：2003-01-21
申请号：US09119355
申请日：1998-07-20
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： C22C2100
CPC分类号： H01L23/53219 , C22C21/00 , H01L23/5221 , H01L2924/0002 , H01L2924/00
摘要： A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

80. 发明授权

US06475899B2 Low capacitance wiring layout and method for making same 有权
标题翻译：低电容布线布局及其制作方法
公开(公告)号：US06475899B2
公开(公告)日：2002-11-05
申请号：US09978071
申请日：2001-10-17
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L214763
CPC分类号： H01L23/522 , H01L23/5222 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.
摘要翻译：描述了设计成抑制电容电阻效应的具有多电平布线布局的集成电路以及制造这种集成电路的方法。集成电路具有彼此相邻并沿相同方向延伸的布线的至少两个平面。一个实施例还可以包括在一个方向上延伸的布线的平面之间的大于正常的绝缘体材料，以及沿与第一方向横向的第二方向延伸的至少一个布线平面。布线平面中的每个布线通道可以相对于在相同方向上延伸的下一相邻布线平面中的相应布线通道偏移。

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