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71. 发明授权

US5890188A Nonvolatile semiconductor memory device having means for selective transfer of memory block contents and for chaining together unused memory blocks 失效
标题翻译：非易失性半导体存储器件具有用于选择性地传送存储块内容并将未连接的存储块连在一起的装置
公开(公告)号：US5890188A
公开(公告)日：1999-03-30
申请号：US948089
申请日：1997-10-09
申请人： Yutaka Okamoto , Yoshiyuki Tanaka
发明人： Yutaka Okamoto , Yoshiyuki Tanaka
IPC分类号： G06F11/10 , G06F12/00 , G06F12/02 , G11C16/02 , G11C16/10 , G11C17/00 , G11C29/00 , G06F12/06
CPC分类号： G11C29/765 , G06F11/1068 , G06F12/0246 , G11C16/102
摘要： A nonvolatile semiconductor memory device using a NAND-type EEPROM includes a memory unit, a management unit, an erasure unit, and a control unit. The memory unit has a memory cell array divided into blocks each constituting a minimum quantity of data that may be erased. The management unit manages unused blocks. The erasure unit discriminates a erased blocks of the unused blocks from a non-erased blocks of the unused blocks to erase data stored in the non-erased blocks. The control unit writes data into at least one block of the unused blocks managed by the management unit. In the control unit, when a content of the written data is obtained by changing data recorded in a different block of the memory unit, and the data recorded in the different block is not necessary, the management unit receives information that the different block is an unused block. When the data recorded in the different block is necessary, a necessary part of the data recorded in the different block is copied to a block in which new data is to be written.
摘要翻译：使用NAND型EEPROM的非易失性半导体存储器件包括存储器单元，管理单元，擦除单元和控制单元。存储器单元具有分成块的存储单元阵列，每个块构成可被擦除的最小数据量。管理单元管理未使用的块。擦除单元从未使用块的未被擦除块识别未使用块的擦除块以擦除存储在未擦除块中的数据。控制单元将数据写入到由管理单元管理的未使用块的至少一个块中。在控制单元中，当通过改变记录在存储单元的不同块中的数据来获得写入数据的内容，并且不需要记录在不同块中的数据时，管理单元接收不同块为未使用的块。当记录在不同块中的数据是必需的时，记录在不同块中的数据的必要部分被复制到要写入新数据的块。

72. 发明授权

US5762051A Exhaust gas recirculation system for an engine 失效
标题翻译：发动机废气再循环系统
公开(公告)号：US5762051A
公开(公告)日：1998-06-09
申请号：US729350
申请日：1996-10-16
申请人： Yutaka Okamoto
发明人： Yutaka Okamoto
IPC分类号： B63H20/24 , F02B61/04 , F02B75/18 , F02B75/22 , F02M25/07
CPC分类号： F02B75/22 , F02B61/045 , F02M26/21 , F02M26/38 , F02M26/41 , F02M26/42 , F02B2075/1824
摘要： An method and device for controlling the NO.sub.x production of an internal combustion engine having at least one cylinder with a cylinder head and an air intake and exhaust passage is disclosed. The device comprises an exhaust gas recirculation system. In a first embodiment, a portion of the exhaust gas produced by the engine is routed through a by-pass line from the exhaust passage through a valve to the air intake passage. In a second embodiment, the by-pass line extends in the space between the two banks of a "V"-type engine along an intake manifold. In a third embodiment, the by-pass line is a passage extending through the cylinder head from an exhaust passage to a valve having an outlet in communication with the air intake passage leading to that cylinder.
摘要翻译：公开了一种用于控制具有至少一个具有气缸盖和进气和排气通道的气缸的内燃机的NOx生成的方法和装置。该装置包括废气再循环系统。在第一实施例中，由发动机产生的排气的一部分通过旁通管线从排气通道经由阀导向进气通道。在第二实施例中，旁路线沿着进气歧管在“V”型发动机的两组之间的空间中延伸。在第三实施例中，旁路线是从排气通道延伸穿过气缸盖的通道，具有与通向该气缸的进气通道连通的出口的阀。

73. 发明授权

US5546351A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5546351A
公开(公告)日：1996-08-13
申请号：US326281
申请日：1994-10-20
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

74. 发明授权

US5477495A Nonvolatile semiconductor memory apparatus 失效
标题翻译：非易失性半导体存储装置
公开(公告)号：US5477495A
公开(公告)日：1995-12-19
申请号：US225926
申请日：1994-04-11
申请人： Yoshiyuki Tanaka , Tomoharu Tanaka , Koji Sakui , Hiroshi Nakamura , Kazunori Ohuchi , Hideko Oodaira , Yutaka Okamoto
发明人： Yoshiyuki Tanaka , Tomoharu Tanaka , Koji Sakui , Hiroshi Nakamura , Kazunori Ohuchi , Hideko Oodaira , Yutaka Okamoto
IPC分类号： G11C16/06 , G11C16/08 , G11C16/10 , G11C16/28 , G11C7/00
CPC分类号： G11C16/08 , G11C16/10 , G11C16/28
摘要： A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.
摘要翻译：本发明的非易失性半导体存储装置的特征在于，在对位线进行充电时，同时执行非选择性存储单元的控制栅极的充电。也就是说，在正常读取（随机存取）的情况下，预选择非选择性存储单元的控制栅极的充电至源极和漏极侧选择栅极中的至少一个。然后，当在读取模式中判断在擦除单元的情况下存储单元的阈值时，通过从非选择性存储单元的控制栅极的充电时间延迟到负极来开始选择栅极的充电。也就是说，选择栅极闭合，直到控制栅极完全设置为负的测试电压，以防止位线被放电。在控制栅极完全设置为负测试电压之后，选择栅极被延迟以被充电，使得选择栅极导通。

75. 发明授权

US5379262A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5379262A
公开(公告)日：1995-01-03
申请号：US84477
申请日：1993-07-01
申请人： Yutaka Okamoto , Yoshiyuki Tanaka
发明人： Yutaka Okamoto , Yoshiyuki Tanaka
IPC分类号： G06F12/02 , G06F3/06 , G06F12/00 , G11C16/02 , G11C16/10 , G11C17/00 , G11C11/40 , G11C13/00
CPC分类号： G06F3/0601 , G11C16/102 , G06F2003/0694
摘要： A nonvolatile semiconductor memory device including a memory means having a plurality of storage areas divided in a capacity serving as a management unit, a first managing means for, when data is to be written in the storage areas, circularly arranging the plurality of storage areas such that the plurality of storage areas physically or logically arranged, and managing the storage areas such that the plurality of storage areas are used in accordance with an order of an arrangement of the plurality of storage areas, a second managing means for managing whether data recorded in the plurality of storage areas is changed after a predetermined timing, and a control means for, when data is written in the storage area and a predetermined condition is satisfied, selecting a storage area having data which is not changed after a timing when the second managing means is initialized, moving the data in the selected storage area to another storage area, and initializing the second managing means when data in all the storage areas are assumed to be changed.
摘要翻译：一种非易失性半导体存储器件，包括具有以用作管理单元的能力划分的多个存储区域的存储装置，当数据要写入存储区域时的第一管理装置，将多个存储区域如多个存储区域物理地或逻辑地布置，并且管理存储区域，使得根据多个存储区域的布置的顺序使用多个存储区域;第二管理装置，用于管理记录在多个存储区域在预定定时之后改变，以及控制装置，当数据被写入存储区域并且满足预定条件时，选择具有在第二管理的定时之后没有改变的数据的存储区域初始化装置，将选择的存储区域中的数据移动到另一个存储区域，并初始化第二管理装置在所有存储区域中的en数据被假定为改变。

76. 发明授权

US5361227A Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US5361227A
公开(公告)日：1994-11-01
申请号：US992653
申请日：1992-12-18
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

77. 发明授权

US5299961A Valve arrangement for an exhaust passage in a marine propulsion unit 失效
标题翻译：用于船用推进单元中的排气通道的阀装置
公开(公告)号：US5299961A
公开(公告)日：1994-04-05
申请号：US962672
申请日：1992-10-19
申请人： Yutaka Okamoto
发明人： Yutaka Okamoto
IPC分类号： B63H20/24 , B63H20/26 , B63H21/32 , B63H23/32 , F01N13/12
CPC分类号： B63H20/245
摘要： A marine propulsion unit includes a cavitation cavity defining a supplemental exhaust gas passage terminating at an exhaust outlet port which is adapted to be opened and closed by a normally closed flapper valve member. The exhaust outlet port includes lateral sidewalls and the flapper valve member includes a fixed portion secured to one of the lateral sidewalls and a cantilevered portion that extends across the exhaust outlet port. The cantilevered portion is adapted to flex relative to the fixed portion so as to open and close the exhaust outlet port in response to dynamic forces acting on the valve member during operation of the watercraft. A stopper plate is provided to limit the deflection of the cantilevered portion of valve member. The cantilevered portion of the valve member is further provided with a fin which projects into the water during operation of the watercraft so that the dynamic pressure of the water acts against the fin the supplement the dynamic pressure exerted on the valve member by the exhaust gas pressure from within the supplemental exhaust passage and to cause the valve to open. When the watercraft is stopped, running at low speeds, decelerating or immediately after planning, the valve will assume a position in which it closes the supplemental exhaust outlet port to reduce exhaust noise.
摘要翻译：船舶推进单元包括空化腔，其限定在排气出口处终止的补充废气通道，该排气口适于由常闭挡板阀构件打开和关闭。排气出口包括侧向侧壁，并且挡板阀构件包括固定到侧壁中的一个侧壁的固定部分和延伸穿过排气出口端口的悬臂部分。悬臂部分适于相对于固定部分弯曲，以响应于在船舶操作期间作用在阀构件上的动力来打开和关闭排气出口。提供止动板以限制阀构件的悬臂部分的偏转。阀构件的悬臂部分还设置有在船舶操作期间向水中突出的翅片，使得水的动态压力通过排气压力补充施加在阀构件上的动态压力在补充排气通道内，并使阀门打开。当船舶停止时，在低速运行，减速或规划后立即运行，阀门将处于关闭补充排气出口端口的位置，以减少排气噪声。

78. 发明授权

US5289404A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5289404A
公开(公告)日：1994-02-22
申请号：US74706
申请日：1993-06-09
申请人： Yutaka Okamoto
发明人： Yutaka Okamoto
IPC分类号： G11C11/417 , G11C5/06
CPC分类号： G11C11/417
摘要： A semiconductor memory device includes a plurality of memory cells arranged along a word line. Each memory cell is constituted by a flip-flop formed by a pair of driver transistors of a first conductivity channel and a pair of load transistors of a second conductivity channel. The load transistors have an active layer formed by a semiconductor thin film.A power line connected to the load transistors includes a first metal layer that extends in a direction parallel to the word line and connections, arranged at intervals along the word line, between the first metal layer and the semiconductor thin film.A ground line is connected to the driver transistors and includes a second metal layer that extends in a direction parallel to the word line and a connecting portion that is connected to the second metal layer and extends in a direction perpendicular to the word line.This arrangement prevents the ON current of the load transistors from being reduced thereby increasing the ON/OFF current ratio without increasing the area required for the memory device. Accordingly, data retention characteristics can be improved without decreasing the degree of circuit integration.
摘要翻译：半导体存储器件包括沿着字线布置的多个存储单元。每个存储单元由由第一导电通道的一对驱动器晶体管和第二导电通道的一对负载晶体管形成的触发器构成。负载晶体管具有由半导体薄膜形成的有源层。连接到负载晶体管的电力线包括在平行于字线的方向上延伸的第一金属层和沿第一金属层和半导体薄膜之间沿着字线间隔设置的连接。接地线连接到驱动晶体管，并且包括沿平行于字线的方向延伸的第二金属层和连接到第二金属层并沿垂直于字线的方向延伸的连接部分。这种布置防止负载晶体管的导通电流减小，从而增加导通/截止电流比，而不增加存储器件所需的面积。因此，可以在不降低电路集成度的情况下提高数据保持特性。

79. 发明授权

US5283200A Method of fabricating complementary semiconductor device 失效
标题翻译：互补半导体器件的制造方法
公开(公告)号：US5283200A
公开(公告)日：1994-02-01
申请号：US918683
申请日：1992-07-27
申请人： Yutaka Okamoto
发明人： Yutaka Okamoto
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L27/0928
摘要： According to this invention, an impurity for forming a P-well region and an impurity for forming an N-channel stopper are sequentially doped in an N-channel region, and an impurity for forming an N-well region and an impurity for forming a P-channel stopper are sequentially doped in a P-channel region. After these impurities are diffused by annealing, an impurity for adjusting a threshold voltage is doped in the entire surface of the resultant structure. As described above, since the doping of these impurities can be performed by steps using a total of two masks, the steps in fabricating a complementary semiconductor device are simple. In addition, since the impurities for forming the well regions and the channel stoppers are diffused by annealing, a large margin against punch through in an element isolation region can be obtained. Furthermore, since the impurity for adjusting a threshold voltage is doped after annealing is performed, diffusion of this impurity is suppressed, thereby minimizing gate swing and the like.
摘要翻译：根据本发明，用于形成P阱区和用于形成N沟道阻挡层的杂质的杂质在N沟道区中顺序地掺杂，并且用于形成N阱区的杂质和用于形成N沟槽的杂质 P沟道阻挡层依次掺杂在P沟道区中。在这些杂质通过退火扩散后，在所得结构的整个表面上掺杂用于调整阈值电压的杂质。如上所述，由于这些杂质的掺杂可以通过使用总共两个掩模的步骤进行，所以制造互补半导体器件的步骤简单。此外，由于用于形成阱区域和通道阻塞物的杂质通过退火而扩散，因此可以获得在元件隔离区域中穿过过大的余量。此外，由于在退火之后掺杂用于调整阈值电压的杂质，所以抑制了该杂质的扩散，从而最小化栅极摆动等。

80. 发明授权

US5073514A Method of manufacturing MIS semiconductor device 失效
标题翻译：制造MIS半导体器件的方法
公开(公告)号：US5073514A
公开(公告)日：1991-12-17
申请号：US553393
申请日：1990-07-17
申请人： Shinichi Ito , Naoya Noshi , Yutaka Okamoto
发明人： Shinichi Ito , Naoya Noshi , Yutaka Okamoto
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L21/2253 , H01L29/6659 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： This invention discloses a method of manufacturing a MIS semiconductor device having at least a portion of a drain region which contacts a channel and has a relatively low impurity concentration to obtain an LDD structure, wherein an insulating film is formed on at least a surface of a semiconductor substrate or double side walls are formed on a gate electrode, the surface is oxidized, and in this state, an impurity region having a relatively high impurity concentration is formed to manufacture a MIS semiconductor device having excellent characteristics at a high yield.

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