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71. 发明授权

US06272619B1 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US06272619B1
公开(公告)日：2001-08-07
申请号：US09437601
申请日：1999-11-10
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

72. 发明授权

US06263423B1 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
标题翻译：用于将非本机指令转换为本地指令以在主机处理器上进行处理的系统和方法
公开(公告)号：US06263423B1
公开(公告)日：2001-07-17
申请号：US09401860
申请日：1999-09-22
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F930
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

73. 发明授权

US06219763B1 System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit 失效
标题翻译：用于调整与寻求访问存储器阵列单元的多个设备相关联的优先级的系统和方法
公开(公告)号：US06219763B1
公开(公告)日：2001-04-17
申请号：US09253760
申请日：1999-02-22
申请人： Derek J. Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Trong Nguyen
发明人： Derek J. Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Trong Nguyen
IPC分类号： G06F1202
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173
摘要： A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include a latch for storing a previous row address request, and a comparator for comparing a previously latched row address request with a present row address request associated with a specific device of the multiple devices seeking access to the MAU. The comparator asserts a row match signal when the previously latched row address request matches the present row address request. The system further includes an arbiter for controlling priorities associated with the multiple devices seeking access to the MAU. The arbiter increases a priority of the specific device when the row match signal is asserted
摘要翻译：一种用于在包括存储器阵列单元（MAU）和寻求访问MAU的多个设备的微处理器架构中传送数据的系统。该系统具有用于检测并指示连续行地址之间的行匹配的行匹配电路。行匹配电路包括用于存储先前行地址请求的锁存器，以及用于将先前锁存的行地址请求与寻求访问MAU的多个设备的特定设备相关联的当前行地址请求进行比较的比较器。当先前锁存的行地址请求与当前的行地址请求相匹配时，比较器会产生一个行匹配信号。该系统还包括用于控制与寻求访问MAU的多个设备相关联的优先级的仲裁器。当行匹配信号被断言时，仲裁器增加特定设备的优先级

74. 发明授权

US6128723A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US6128723A
公开(公告)日：2000-10-03
申请号：US309603
申请日：1999-05-11
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

75. 发明授权

US6092181A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US6092181A
公开(公告)日：2000-07-18
申请号：US946078
申请日：1997-10-07
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

76. 发明授权

US6083274A Integrated structure layout and layout of interconnections for an integrated circuit chip 有权
标题翻译：用于集成电路芯片的指令执行单元的集成结构布局和互连布局
公开(公告)号：US6083274A
公开(公告)日：2000-07-04
申请号：US173560
申请日：1998-10-16
申请人： Kevin R. Iadonato , Le Trong Nguyen
发明人： Kevin R. Iadonato , Le Trong Nguyen
IPC分类号： G06F5/00 , G06F7/00 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/40 , G06F15/00 , G06F15/76 , G06F17/00 , G06F17/50 , G06F19/00 , H01L21/82 , H01L27/00
CPC分类号： G06F9/30141 , G06F17/5068 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information output to the tag assignment logic. The tag assignment logic provides tag information output to the register file port multiplexer logic. The tag assignment logic is arranged on opposite sides of a center channel, so that the tag information output is laid-out in the center channel and is fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information output to a register file address port of a register file.
摘要翻译：用于集成电路芯片的集成执行单元的功能块和互连的集成结构布局。集成执行单元的功能块包括数据依赖比较器逻辑，标签分配逻辑和寄存器文件端口复用器逻辑。数据依赖逻辑接收一组指令的地址信号，并将输出的依赖信息传递给标签分配逻辑。标签分配逻辑提供输出到寄存器文件端口多路复用器逻辑的标签信息。标签分配逻辑被布置在中心信道的相对侧上，使得标签信息输出在中心信道中布置，并且以基本上直的路径直接馈送到寄存器文件端口多路复用器逻辑。寄存器文件端口多路复用器逻辑将标签信息输出引导到寄存器文件的寄存器文件地址端口。

77. 发明授权

US6038654A High performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US6038654A
公开(公告)日：2000-03-14
申请号：US338563
申请日：1999-06-23
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

78. 发明授权

US5778434A System and method for processing multiple requests and out of order returns 失效
标题翻译：用于处理多个请求和无序返回的系统和方法
公开(公告)号：US5778434A
公开(公告)日：1998-07-07
申请号：US479035
申请日：1995-06-07
申请人： Le Trong Nguyen , Yasuaki Hagiwara
发明人： Le Trong Nguyen , Yasuaki Hagiwara
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F12/0857
摘要： A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where the data is stored. Cache-control ID tags are assigned to identify the locations in the request queue of the respective CPU-ID tags associated with each CPU request. Cache-control requests consisting of the cache-control ID tags and the respective address information are sent from the request queue to the lower-level memory or storage devices. Data is then returned along with the corresponding CCU-ID tags in the order in which it is returned by the storage devices. Finally, the sequence of CPU requests for data is fulfilled by returning the data and CPU-ID tag in the order in which the data was returned from lower-level memory. By issuing multiple requests for data and allowing out of order data return, data is retrieved from lower-level memory after cache misses more quickly and efficiently than processing data requests in sequence. By checking the request queue, pending CPU requests for the same data including requests for the same long word of data can be identified. Cache hits for multiple requests are determined by simultaneously checking sets in cache memory. Multiple instructions are then issued for multiple superset cache hits.
摘要翻译：一种用于在高速缓存未命中之后由一个或多个中央处理单元（CPU）处理数据请求序列的系统和方法。每个CPU请求包括标识发出数据请求的CPU的CPU-ID标签和标识存储数据的下级存储器中的位置的地址。分配缓存控制ID标签来标识与每个CPU请求相关联的相应CPU-ID标签的请求队列中的位置。由缓存控制ID标签和相应地址信息组成的缓存控制请求从请求队列发送到下级存储器或存储设备。数据随着相应的CCU-ID标签按照存储设备返回的顺序返回。最后，按照从低级内存返回数据的顺序返回数据和CPU-ID标签来满足CPU请求数据的顺序。通过对数据发出多个请求并允许无序数据返回，在缓存错过比缓冲区顺序地处理数据请求更快，更有效率之后，从低级存储器检索数据。通过检查请求队列，可以识别对同一数据的待处理CPU请求，包括对同一长字数据的请求。通过同时检查高速缓存中的集合来确定多个请求的高速缓存命中。然后针对多个超集高速缓存命中发出多条指令。

79. 发明授权

US5754800A Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption 失效
标题翻译：具有基于先前服务地址的行匹配的动态优先级的多处理器系统，拒绝服务的次数和不间断地服务的次数
公开(公告)号：US5754800A
公开(公告)日：1998-05-19
申请号：US442649
申请日：1995-05-16
申请人： Derek J. Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Trong Nguyen
发明人： Derek J. Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Trong Nguyen
IPC分类号： G06F9/46 , G06F9/52 , G06F12/00 , G06F12/02 , G06F12/06 , G06F12/08 , G06F13/18 , G06F13/362 , G06F13/40 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/177 , G06F13/14
CPC分类号： G06F12/0813 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173 , G06F12/0215 , G06F12/0831
摘要： A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network and interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing the priority of the devices based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.
摘要翻译：一种包括能够支持多个处理器的多处理器架构的计算机系统，包括存储器阵列单元（MAU），包括数据，地址和控制信号总线的MAU系统总线，包括数据，地址和控制信号总线的I / O总线，多个的I / O设备和多个微处理器。数据和指令高速缓存和I / O设备之间的数据传输以及存储器和其他I / O设备使用交换机网络和接口电路进行处理。存储器总线的访问由使用固定和动态优先级方案的仲裁电路控制。提供了一种行匹配比较电路，用于通过对具有相同行地址的存储器位置的连续请求提供更高的优先级来减少存储器等待时间。通过基于设备的内在优先级，基于行匹配的服务请求次数，设备被拒绝服务的次数来改变设备的优先级来提供动态切换/端口仲裁，以及设备已被维护的次数。

80. 发明授权

US5682546A RISC microprocessor architecture implementing multiple typed register sets 失效
标题翻译： RISC微处理器架构实现多种类型的寄存器集
公开(公告)号：US5682546A
公开(公告)日：1997-10-28
申请号：US665845
申请日：1996-06-19
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48 , G06F15/00
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA�23:0!) and second (RA�31:24!) subsets, and a shadow subset (RT�31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
摘要翻译：一种用于以多种模式操作的数据处理器的寄存器系统。寄存器系统提供多个相同的寄存器组，数据处理器控制访问，使得指令和过程不需要指定任何给定的存储体。整数寄存器集包括第一（RA [23：0]）和第二（RA [31:24]）子集和影子子集（RT [31:24]）。当数据处理器处于第一模式时，指令访问第一和第二子集。当数据处理器处于第二模式时，指令可以访问第一子集，但是任何访问第二子集的尝试都被重新路由到阴影子集，而不是透明地指向该指令，从而允许系统例程看起来使用第二子集，而没有必须保存和恢复哪个用户例程已写入第二个子集的数据。重分类寄存器组分别提供整数宽度数据和浮点宽度数据，以响应整数指令和浮点指令。布尔比较指令为要比较的源数据指定特定的整数或浮点寄存器，并为结果指定一个特定的布尔寄存器，因此没有专用的固定位置状态标志。布尔组合指令组合指定的布尔寄存器，用于执行复杂的布尔比较而无需干预条件分支指令，以最大限度地减少管道中断。

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