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71. 发明申请

US20110227159A1 THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE 失效
标题翻译：薄盒金属背板超薄SOI器件
公开(公告)号：US20110227159A1
公开(公告)日：2011-09-22
申请号：US12724555
申请日：2010-03-16
申请人： Kevin K. Chan , Zhibin Ren , Xinhui Wang
发明人： Kevin K. Chan , Zhibin Ren , Xinhui Wang
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/7827 , H01L21/7624 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.
摘要翻译：使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。 ETSOI器件使用由薄氮化物层封装的薄钨背栅来制造，以防止金属氧化，钨背栅的特征在于其低电阻率。该结构还包括至少一个FET，其具有由高K金属栅极和叠加在其上的钨区域形成的栅极堆叠，栅极堆叠的占用面积利用薄SOI层作为沟道。这样形成的SOI结构控制了薄SOI厚度和其中的掺杂剂的Vt变化。 ETSOI高K金属后盖完全耗尽器件与薄BOX结合，提供了出色的短通道控制，显着降低了漏极引起的偏置和次阈值摆幅。本结构支持在热处理期间具有钨膜的晶片的稳定性的证据，特别是在STI和接触形成期间。

72. 发明申请

US20110180872A1 ASYMMETRIC EPITAXY AND APPLICATION THEREOF 有权
公开(公告)号：US20110180872A1
公开(公告)日：2011-07-28
申请号：US13080702
申请日：2011-04-06
申请人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
发明人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
IPC分类号： H01L29/772
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

73. 发明申请

US20110095343A1 BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT 有权
标题翻译：双层NFET嵌入式应力元件和集成以增强驱动电流
公开(公告)号：US20110095343A1
公开(公告)日：2011-04-28
申请号：US12607104
申请日：2009-10-28
申请人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

74. 发明申请

US20110062518A1 finFETS AND METHODS OF MAKING SAME 有权
公开(公告)号：US20110062518A1
公开(公告)日：2011-03-17
申请号：US12561606
申请日：2009-09-17
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

75. 发明授权

US07897960B2 Self-aligned nanotube field effect transistor 有权
标题翻译：自对准纳米管场效应晶体管
公开(公告)号：US07897960B2
公开(公告)日：2011-03-01
申请号：US12544412
申请日：2009-08-20
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L29/76 , H01L29/06 , H01L29/94
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

76. 发明申请

US20110027948A1 METHOD FOR MANUFACTURING A FINFET DEVICE 有权
标题翻译：制造FINFET器件的方法
公开(公告)号：US20110027948A1
公开(公告)日：2011-02-03
申请号：US12533389
申请日：2009-07-31
申请人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
发明人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.
摘要翻译：一种制造FinFET器件的方法包括：提供其上设置有掩模的衬底; 覆盖掩模的部分以限定栅极区域的周边; 去除所述掩模的未覆盖部分以暴露所述基底; 用另一掩模覆盖暴露的基底的一部分以限定至少一个鳍片区域; 通过所述掩模和所述基板形成所述至少一个翅片和所述栅极区域，所述栅极区域具有侧壁; 将所述至少一个翅片周围的绝缘层设置在所述侧壁上; 将导电材料设置在栅极区域和绝缘层上以形成栅电极，然后形成源极和漏极区域。

77. 发明申请

US20090309092A1 SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME 有权
标题翻译：自对准纳米管场效应晶体管及其制备方法
公开(公告)号：US20090309092A1
公开(公告)日：2009-12-17
申请号：US12544412
申请日：2009-08-20
申请人： JOERG APPENZELLER , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： JOERG APPENZELLER , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L29/12
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

78. 发明授权

US07566631B2 Low temperature fusion bonding with high surface energy using a wet chemical treatment 失效
标题翻译：使用湿化学处理的低表面能低温熔接
公开(公告)号：US07566631B2
公开(公告)日：2009-07-28
申请号：US11411395
申请日：2006-04-26
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够在低温（小于或等于400℃）下将诸如半导体（例如Si）的两个晶片极度直接结合到绝缘体（例如SiO 2）。使用这些表面处理中的一些已经实现了接合界面的高达〜4835±675mJ / m 2的表面能。该值与显着更高的处理温度（小于1000℃）报告的值相当。这里也可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙结合界面。

79. 发明授权

US07498640B2 Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby 失效
公开(公告)号：US07498640B2
公开(公告)日：2009-03-03
申请号：US10437930
申请日：2003-05-15
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

80. 发明授权

US07442612B2 Nitride-encapsulated FET (NNCFET) 有权
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07442612B2
公开(公告)日：2008-10-28
申请号：US11481532
申请日：2006-07-06
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

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