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    • 72. 发明授权
    • Self aligned LOD antiblooming structure for solid-state imagers
    • 固态成像器的自对准LOD防护结构
    • US6051852A
    • 2000-04-18
    • US891290
    • 1997-07-10
    • Eric G. Stevens
    • Eric G. Stevens
    • H01L27/148H01L29/768
    • H01L27/14887
    • A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.
    • 自对准的横向溢流漏极防护结构对漏极偏置电压不敏感,因此对工艺变化的不敏感性提高。 通过光刻可以容易地调节和确定防起泡屏障区域的长度。 自对准的横向溢流排水(LOD)防爆结构导致节省空间的设计,从而提高整体传感器性能。 在这种结构中,提供了比将像素彼此分开的屏障更小(伏特)的抗电势势垒,使得与相邻像素相反,过量电荷优先流入LOD。
    • 74. 发明授权
    • Image sensor with improved output region for superior charge transfer
characteristics
    • 图像传感器具有改进的输出区域,具有出色的电荷转移特性
    • US5514886A
    • 1996-05-07
    • US374280
    • 1995-01-18
    • Eric G. StevensJames P. Lavine
    • Eric G. StevensJames P. Lavine
    • H01L21/339H01L27/148H01L29/762H01L29/768H04N5/372H04N5/378
    • H01L29/76816H01L27/14831
    • The new CCD output region provides a method of reducing the width of a wide CCD at its output to maintain a high sensitivity output node without sacrificing charge-transfer efficiency. A barrier region is shaped so the "channel width" of the CCD increases towards the input edge of the output gate. The barrier region, therefore, decreases in width towards the output end of the final CCD phase of a multi-phase device. Also, the channel width under the output gate decreases towards its output end in the direction of charge transfer towards the floating diffusion, or detection node. Since the "shaped" portion of the barrier region under the last CCD phase can be formed by the same process steps as the regular-shaped barrier regions, it is possible to form this structure without the requirement for additional masking and implant steps. The advantages of this structure over the prior art are improved charge-transfer characteristics without requiring additional process steps.
    • 新的CCD输出区域提供了在其输出端减小宽CCD的宽度以维持高灵敏度输出节点而不牺牲电荷传输效率的方法。 阻挡区域的形状使得CCD的“通道宽度”朝向输出门的输入边缘增加。 因此,阻挡区域的宽度朝向多相设备的最终CCD相的输出端减小。 此外,输出栅极下的沟道宽度朝向浮动扩散或检测节点的电荷转移方向朝向其输出端减小。 由于最后CCD相位下的阻挡区域的“成形”部分可以通过与正常形状的阻挡区域相同的工艺步骤形成,所以可以形成这种结构,而不需要额外的掩模和注入步骤。 与现有技术相比,该结构的优点是改进的电荷转移特性,而不需要额外的工艺步骤。
    • 75. 发明授权
    • Method of making two-phase buried channel planar gate CCD
    • 制造两相埋管平面栅极CCD的方法
    • US5298448A
    • 1994-03-29
    • US995393
    • 1992-12-18
    • Eric G. StevensStephen L. Kosman
    • Eric G. StevensStephen L. Kosman
    • H01L29/762H01L21/339H01L29/768
    • H01L29/66954H01L29/76841Y10S438/947
    • The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.
    • 本发明涉及一种使用用于栅电极的导电材料的单层(层)制造真正的两相CCD以提供平面结构的方法。 该方法包括在导电层的表面上并沿间隔开的二氧化硅屏蔽层之间使用具有底部的亚微米长度的L形掩模层。 导电层与其中具有沟道区的半导体材料的主体的表面结合并绝缘。 去除L形掩模层以露出导电层的间隔的狭窄部分。 然后,在每个暴露部分,完全蚀刻导电层,以将导电层划分成由亚微米宽度间隔间隔开的栅电极。