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71. 发明授权

US08886868B2 Memory system and control method thereof 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US08886868B2
公开(公告)日：2014-11-11
申请号：US12778484
申请日：2010-05-12
申请人： Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
发明人： Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0647 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F2212/1036 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
摘要： A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
摘要翻译：存储器系统包括包括作为数据擦除单元的多个块的非易失性存储器，测量擦除每个块的数据的擦除时间的测量单元，以及写入从至少外部提供的数据到第一块设置为空闲状态，擦除时间最长。

72. 发明授权

US08418042B2 Semiconductor memory device 有权
公开(公告)号：US08418042B2
公开(公告)日：2013-04-09
申请号：US12889018
申请日：2010-09-23
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G06F11/1012 , G06F11/1072 , G06F11/1076 , G11C16/10 , G11C29/52 , G11C2029/0411 , H03M13/1515 , H03M13/29 , H03M13/2906
摘要： A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

73. 发明申请

US20120179942A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20120179942A1
公开(公告)日：2012-07-12
申请号：US13426696
申请日：2012-03-22
申请人： Yasushi NAGADOMI , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
发明人： Yasushi NAGADOMI , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
IPC分类号： G06F11/26
CPC分类号： G11C16/349 , G06F11/008 , G06F11/1068
摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
摘要翻译：提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数，诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

74. 发明授权

US08196008B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08196008B2
公开(公告)日：2012-06-05
申请号：US13090539
申请日：2011-04-20
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

75. 发明授权

US08117517B2 Semiconductor memory device and method of controlling the same 有权
公开(公告)号：US08117517B2
公开(公告)日：2012-02-14
申请号：US12404861
申请日：2009-03-16
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

76. 发明申请

US20110219177A1 MEMORY SYSTEM AND CONTROL METHOD THEREOF 审中-公开
标题翻译：存储系统及其控制方法
公开(公告)号：US20110219177A1
公开(公告)日：2011-09-08
申请号：US13107623
申请日：2011-05-13
申请人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
发明人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
IPC分类号： G06F12/06
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/52 , G11C29/76
摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.
摘要翻译：一种存储器系统，包括：包括作为数据擦除单元的块的非易失性存储器，测量擦除每个块中的数据的擦除时间的测量单元;具有块表的块控制器，其将指示空闲状态之一的状态值和具有每个块的擦除时间的使用状态，检测在短时间内共同发生重写的块的检测器，选择具有旧擦除时间的空闲块作为第一块的第一选择器，选择如果第一块被包括在由检测器检测到的块中，则将具有旧擦除时间的块用作第二块;以及调平单元，其将第二块中的数据移动到第一块。

77. 发明授权

US07949910B2 Memory system and control method thereof 有权
公开(公告)号：US07949910B2
公开(公告)日：2011-05-24
申请号：US12705431
申请日：2010-02-12
申请人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
发明人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
IPC分类号： G11C29/00 , G06F13/00 , G06F13/28
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/76
摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.

78. 发明授权

US07848143B2 Memory controller controlling semiconductor storage device and semiconductor device 失效
标题翻译：存储控制器控制半导体存储器件和半导体器件
公开(公告)号：US07848143B2
公开(公告)日：2010-12-07
申请号：US12687915
申请日：2010-01-15
申请人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
发明人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.
摘要翻译：存储器控制器控制包括非易失性存储单元的半导体存储器件。控制器包括发生电路和选择电路。生成电路基于第二数据生成第一数据。选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。选择电路选择第一数据之一。所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。选择电路将与所选择的第一数据相关的和保持为新的累积值。

79. 发明授权

US07644297B2 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US07644297B2
公开(公告)日：2010-01-05
申请号：US11819417
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/04 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。

80. 发明授权

US07496811B2 Storage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage medium 失效
标题翻译：存储介质再现装置，存储介质再现方法和用于从存储介质读取信息的计算机程序产品
公开(公告)号：US07496811B2
公开(公告)日：2009-02-24
申请号：US11360604
申请日：2006-02-24
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B20/18 , G11B27/36
摘要： A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit. The correcting unit performs a correcting operation using an error correction code on the corrected information, and registers the correction history of the corrected information storage unit.
摘要翻译：存储介质再现装置包括存储单元，校正历史存储单元，校正历史实现单元和校正单元。存储单元包括多个信息存储单元，其存储取决于计费量是否大于预定电荷量阈值的信息;以及校正码存储单元，存储存储在信息存储单元中的信息的纠错码。校正历史存储单元存储包含用纠错码校正的信息存储单元的识别信息的校正历史，以及校正的内容。当从信息存储单元读取信息时，校正历史实现单元根据校正的内容校正信息。校正单元使用校正信息上的纠错码执行校正操作，并且登记校正信息存储单元的校正历史。

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