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1. 发明授权

US09128864B2 Memory controller, storage device and error correction method 有权
标题翻译：存储控制器，存储设备和纠错方法
公开(公告)号：US09128864B2
公开(公告)日：2015-09-08
申请号：US13724337
申请日：2012-12-21
申请人： Osamu Torii , Shinichi Kanno
发明人： Osamu Torii , Shinichi Kanno
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1044
摘要： According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.
摘要翻译：根据一个实施例，存储器控制器包括编码单元，其为每个用户数据生成第一奇偶校验，并且为两个或更多个用户数据生成第二奇偶校验，以及相应的第一奇偶校验，存储器接口单元，读出来自非易失性存储器的用户数据和奇偶校验，以及使用用户数据和奇偶校验执行纠错解码处理的解码单元。使用第一奇偶校验和第二奇偶校验两者的纠错解码处理至少具有用于第一用户数据的校正能力的A（第一奇偶校正能力）+ B（第二奇偶校验的校正能力）比特及其第一和第二奇偶校验以及第二用户数据及其第一和第二奇偶校验。

2. 发明授权

US08812774B2 Memory system and computer program product 有权
标题翻译：内存系统和计算机程序产品
公开(公告)号：US08812774B2
公开(公告)日：2014-08-19
申请号：US13217461
申请日：2011-08-25
申请人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
发明人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1068
摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
摘要翻译：根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子接收单元; 发电机组; 第二个表和书写单位。第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

3. 发明授权

US08640013B2 Storage device 失效
标题翻译：储存设备
公开(公告)号：US08640013B2
公开(公告)日：2014-01-28
申请号：US13601707
申请日：2012-08-31
申请人： Toshikatsu Hida , Shinichi Kanno , Osamu Torii , Koji Horisaki , Dong Zhang
发明人： Toshikatsu Hida , Shinichi Kanno , Osamu Torii , Koji Horisaki , Dong Zhang
IPC分类号： H03M13/15
CPC分类号： G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/159 , H03M13/3715 , H03M13/3746
摘要： According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.
摘要翻译：根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

4. 发明授权

US08612824B2 Semiconductor memory device and controlling method 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08612824B2
公开(公告)日：2013-12-17
申请号：US13038804
申请日：2011-03-02
申请人： Kazumasa Yamamoto , Shinichi Kanno , Shigehiro Asano , Hiroyuki Nagashima
发明人： Kazumasa Yamamoto , Shinichi Kanno , Shigehiro Asano , Hiroyuki Nagashima
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.
摘要翻译：半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。

5. 发明申请

US20130305120A1 MEMORY CONTROLLER, STORAGE DEVICE AND ERROR CORRECTION METHOD 有权
标题翻译：存储控制器，存储设备和错误校正方法
公开(公告)号：US20130305120A1
公开(公告)日：2013-11-14
申请号：US13724337
申请日：2012-12-21
申请人： Osamu TORII , Shinichi Kanno
发明人： Osamu TORII , Shinichi Kanno
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1044
摘要： According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.
摘要翻译：根据一个实施例，存储器控制器包括编码单元，其为每个用户数据生成第一奇偶校验，并且为两个或更多个用户数据生成第二奇偶校验，以及相应的第一奇偶校验，存储器接口单元，读出来自非易失性存储器的用户数据和奇偶校验，以及使用用户数据和奇偶校验执行纠错解码处理的解码单元。使用第一奇偶校验和第二奇偶校验两者的纠错解码处理至少具有用于第一用户数据的校正能力的A（第一奇偶校正能力）+ B（第二奇偶校验的校正能力）比特及其第一和第二奇偶校验以及第二用户数据及其第一和第二奇偶校验。

6. 发明申请

US20130254637A1 ENCODING APPARATUS, CONTROL METHOD OF ENCODING APPARATUS, AND MEMORY DEVICE 有权
标题翻译：编码装置，编码装置的控制方法和存储装置
公开(公告)号：US20130254637A1
公开(公告)日：2013-09-26
申请号：US13600929
申请日：2012-08-31
申请人： Yoshiki Saito , Shinichi Kanno , Toshikatsu Hida
发明人： Yoshiki Saito , Shinichi Kanno , Toshikatsu Hida
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , H03M13/6516
摘要： According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.
摘要翻译：根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

7. 发明授权

US08438454B2 Semiconductor memory device and controlling method 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08438454B2
公开(公告)日：2013-05-07
申请号：US13218743
申请日：2011-08-26
申请人： Shinichi Kanno , Osamu Torii
发明人： Shinichi Kanno , Osamu Torii
IPC分类号： G11C29/00
CPC分类号： G06F11/1016 , G06F12/0246 , G06F2212/1032 , G06F2212/7201
摘要： According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information.
摘要翻译：根据实施例，半导体存储器件包括非易失性存储器; 输入/输出控制单元，用于控制与非易失性存储器的数据的输入/输出; 地址转换表，其将指定存储在所述非易失性存储器中的用户数据的逻辑记录位置的第一地址信息与表示所述非易失性存储器中的物理记录位置的第二地址信息相关联; 翻译单元，用于根据该表将第一地址信息转换为第二地址信息; 以及生成单元，用于生成用于检查用户数据中是否存在错误的冗余数据以及用作一个数据段的第一地址信息。输入/输出控制单元在由第二地址信息表示的非易失性存储器中的物理记录位置中记录用作一个数据集的用户数据，第一地址信息和冗余数据作为数据集。

8. 发明授权

US08397017B2 Controller and data storage device 有权
标题翻译：控制器和数据存储设备
公开(公告)号：US08397017B2
公开(公告)日：2013-03-12
申请号：US12723846
申请日：2010-03-15
申请人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0679 , G06F2212/7207
摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
摘要翻译：易失性管理存储器存储用于管理存储介质的使用状态的管理信息。管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息处理内容，并创建表示管理信息的更新内容的日志。日志存储单元将日志存储在存储介质中。恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。

9. 发明授权

US08281192B2 Storage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage medium 有权
标题翻译：存储介质再现装置，存储介质再现方法和用于从存储介质读取信息的计算机程序产品
公开(公告)号：US08281192B2
公开(公告)日：2012-10-02
申请号：US12354934
申请日：2009-01-16
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B20/18 , G11B27/36
摘要： A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit. The correcting unit performs a correcting operation using an error correction code on the corrected information, and registers the correction history of the corrected information storage unit.
摘要翻译：存储介质再现装置包括存储单元，校正历史存储单元，校正历史实现单元和校正单元。存储单元包括多个信息存储单元，其存储取决于计费量是否大于预定电荷量阈值的信息;以及校正码存储单元，存储存储在信息存储单元中的信息的纠错码。校正历史存储单元存储包含用纠错码校正的信息存储单元的识别信息的校正历史，以及校正的内容。当从信息存储单元读取信息时，校正历史实现单元根据校正的内容校正信息。校正单元使用校正信息上的纠错码执行校正操作，并且登记校正信息存储单元的校正历史。

10. 发明授权

US08156393B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08156393B2
公开(公告)日：2012-04-10
申请号：US12513860
申请日：2007-11-28
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
IPC分类号： G11C29/00
CPC分类号： G11C16/349 , G06F11/008 , G06F11/1068
摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
摘要翻译：提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数，诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

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