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71. 发明授权

US07659564B2 CMOS imager photodiode with enhanced capacitance 失效
标题翻译：具有增强电容的CMOS成像光电二极管
公开(公告)号：US07659564B2
公开(公告)日：2010-02-09
申请号：US11276085
申请日：2006-02-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/04
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间并形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

72. 发明申请

US20090286346A1 Methods For Forming Anti-Reflection Structures For CMOS Image Sensors 有权
标题翻译： CMOS图像传感器形成防反射结构的方法
公开(公告)号：US20090286346A1
公开(公告)日：2009-11-19
申请号：US12120459
申请日：2008-05-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/0236 , H01L31/18
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

73. 发明申请

US20090261415A1 FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) 有权
标题翻译：具有反向短路通道效应（SCE）的全自动低体积场效应晶体管（FET）由自对准边缘背栅（S）
公开(公告)号：US20090261415A1
公开(公告)日：2009-10-22
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L49/00 , H01L21/00
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

74. 发明申请

US20090179232A1 LOW LAG TRANSFER GATE DEVICE 有权
标题翻译： LOW LAG传输闸门装置
公开(公告)号：US20090179232A1
公开(公告)日：2009-07-16
申请号：US12013817
申请日：2008-01-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14612
摘要： A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.
摘要翻译： CMOS有源像素传感器（APS）单元结构包括至少一个传输栅极器件和操作方法。第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

75. 发明授权

US07446007B2 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof 失效
标题翻译：具有抑制凹陷/底切的多层间隔物及其制造方法
公开(公告)号：US07446007B2
公开(公告)日：2008-11-04
申请号：US11560893
申请日：2006-11-17
申请人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
发明人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
摘要翻译：半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。因此确保了多层间隔层的尺寸完整性和分层避免。

76. 发明申请

US20080150147A1 HIGH SURFACE AREA ALUMINUM BOND PAD FOR THROUGH-WAFER CONNECTIONS TO AN ELECTRONIC PACKAGE 有权
标题翻译：高表面积的铝合金焊盘，用于通过电缆连接到电子包装
公开(公告)号：US20080150147A1
公开(公告)日：2008-06-26
申请号：US12046737
申请日：2008-03-12
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L23/488
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

77. 发明申请

US20080002316A1 POWER CLAMP DEVICES WITH VERTICAL NPN DEVICES 审中-公开
标题翻译：具有垂直NPN器件的电源钳位器件
公开(公告)号：US20080002316A1
公开(公告)日：2008-01-03
申请号：US11427063
申请日：2006-06-28
申请人： James W. Adkisson , John J. Ellis-Monaghan , Steven H. Voldman
发明人： James W. Adkisson , John J. Ellis-Monaghan , Steven H. Voldman
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： ESD power clamp devices with vertical NPN devices are disclosed. The power clamp is formed on an N type substrate and includes an N channel field effect transistor (NFET). The source and drain regions of the NFET, a P type epitaxial region under the NFET, and the N type substrate constitutes two vertical NPN devices. As such, vertical interactions of electrons are enabled to avoid the disadvantages of traditional power clamps, e.g., minority carrier cross-talk.
摘要翻译：公开了具有垂直NPN器件的ESD功率钳位器件。电源钳位形成在N型衬底上并且包括N沟道场效应晶体管（NFET）。 NFET的源极和漏极区域，NFET下的P型外延区域和N型衬底构成两个垂直NPN器件。因此，电子的垂直相互作用能够避免传统功率钳位的缺点，例如少数载流子串扰。

78. 发明授权

US07265417B2 Method of fabricating semiconductor side wall fin 有权
公开(公告)号：US07265417B2
公开(公告)日：2007-09-04
申请号：US10867772
申请日：2004-06-16
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

79. 发明授权

US07205627B2 Image sensor cells 有权
标题翻译：图像传感器单元
公开(公告)号：US07205627B2
公开(公告)日：2007-04-17
申请号：US10906510
申请日：2005-02-23
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
IPC分类号： H01L31/06
CPC分类号： H01L27/14609 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L31/035281
摘要： A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.
摘要翻译：用于图像传感器单元的结构（及其形成方法）。该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

80. 发明授权

US07129130B2 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US07129130B2
公开(公告)日：2006-10-31
申请号：US11298800
申请日：2005-12-09
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242 , H01L2/20
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

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