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71. 发明授权

US07538633B2 Method and apparatus for driving on-chip wires through capacitive coupling 有权
标题翻译：通过电容耦合驱动片上导线的方法和装置
公开(公告)号：US07538633B2
公开(公告)日：2009-05-26
申请号：US10953008
申请日：2004-09-28
申请人： Robert J. Drost , Ronald Ho , Tarik Ono
发明人： Robert J. Drost , Ronald Ho , Tarik Ono
IPC分类号： H01P5/00 , H03H7/00
CPC分类号： H04L25/0266
摘要： One embodiment of the present invention provides a system which drives on-chip wires using capacitive coupling. During operation, the system drives a signal onto a driven wire. This signal feeds from the driven wire through a coupling capacitor onto a coupled wire, which is an on-chip wire that routes the signal to its destination. Feeding the signal through the coupling capacitor reduces the voltage swing of the corresponding coupled signal on the coupled wire, thereby lessening the power required to drive the coupled signal on the coupled wire.
摘要翻译：本发明的一个实施例提供一种使用电容耦合来驱动片上导线的系统。在操作期间，系统将信号驱动到从动电线上。该信号从驱动线通过耦合电容器馈送到耦合线，该耦合线是将信号路由到其目的地的片上线。通过耦合电容馈送信号可以减小耦合线上相应耦合信号的电压摆幅，从而减少驱动耦合线上耦合信号所需的功率。

72. 发明授权

US07123038B1 Method and apparatus for performing on-chip sampling over an extended voltage range 有权
标题翻译：用于在扩展电压范围内进行片上采样的方法和装置
公开(公告)号：US07123038B1
公开(公告)日：2006-10-17
申请号：US10739473
申请日：2003-12-17
申请人： Ronald Ho , Robert J. Drost
发明人： Ronald Ho , Robert J. Drost
IPC分类号： G01R31/02 , H03K5/22
CPC分类号： G11C27/02 , G01R19/2503
摘要： One embodiment of the present invention provides a system that performs voltage sampling over an extended voltage range on a semiconductor chip. During operation, the system receives an input voltage at a node within the semiconductor chip. The system samples the input voltage through a first sampling pathway using NMOS pass gates, which latch the input voltage to produce a first output signal. This first output signal tracks the input voltage from ground up to a cut-off voltage for the nMOS pass gates. The system also samples the input voltage through a second sampling pathway using nMOS pass gates, which latch the input voltage to produce a second output signal. Prior to the NMOS pass gates along the second sampling pathway, the input voltage passes through a source-follower gate, which translates the input voltage down, so that the second output signal tracks the input voltage from a turn-on voltage of the source-follower gate up to Vdd. Next, the system combines the first and second output signals to produce a combined output signal, which tracks the input voltage over the extended voltage range from ground to Vdd.
摘要翻译：本发明的一个实施例提供了一种在半导体芯片上的扩展电压范围内执行电压采样的系统。在操作期间，系统在半导体芯片内的节点处接收输入电压。该系统通过使用NMOS通道栅极的第一采样通道对输入电压进行采样，锁存输入电压以产生第一输出信号。该第一输出信号跟踪nMOS通过门的接地直到输入电压为截止电压。该系统还通过使用nMOS通过门的第二采样通道对输入电压进行采样，门控锁存输入电压以产生第二输出信号。在沿着第二采样路径的NMOS通道门之前，输入电压通过源极跟随器栅极，其将输入电压降低，使得第二输出信号从源极 - 漏极栅极的导通电压跟踪输入电压，跟随器门高达V dd。接下来，该系统组合第一和第二输出信号以产生组合的输出信号，该信号跟踪从接地到V DD的扩展电压范围内的输入电压。

73. 发明授权

US07067910B2 Method and apparatus for using capacitively coupled communication within stacks of laminated chips 有权
公开(公告)号：US07067910B2
公开(公告)日：2006-06-27
申请号：US10966510
申请日：2004-10-14
申请人： Robert J. Drost , Ronald Ho , Arthur R. Zingher
发明人： Robert J. Drost , Ronald Ho , Arthur R. Zingher
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/0652 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.

74. 发明授权

US07030470B1 Using chip lamination to couple an integrated circuit with a microstrip transmission line 有权
标题翻译：使用芯片层压将集成电路与微带传输线耦合
公开(公告)号：US07030470B1
公开(公告)日：2006-04-18
申请号：US10844196
申请日：2004-05-11
申请人： Ronald Ho , Robert J. Drost , Chih-Kong Ken Yang
发明人： Ronald Ho , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H01L39/00
CPC分类号： H01L23/66 , H01L23/481 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/82 , H01L24/83 , H01L2223/6627 , H01L2224/2402 , H01L2224/48091 , H01L2224/4813 , H01L2224/49175 , H01L2224/4943 , H01L2224/81193 , H01L2224/81801 , H01L2224/83894 , H01L2924/00014 , H01L2924/14 , H01L2924/1903 , H01L2924/30107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.
摘要翻译：本发明的一个实施例提供了一种通过芯片层压将集成电路与微带传输线可操作地耦合的系统。该系统包括包含集成电路的第一半导体管芯和包含微带传输线的第二半导体管芯。与集成电路中具有相对小的横截面的金属线不同，微带传输线具有足够大的横截面，使得信号传播由电感和电容（LC）代替电阻和电容（RC）来控制，。将第一半导体管芯和第二半导体管芯层叠在一起，使得第一半导体管芯上的集成电路与第二半导体管芯中的微带传输线可操作地耦合。

75. 发明授权

US08975752B2 Multiple access over proximity communication 有权
标题翻译：通过近距离通信多次访问
公开(公告)号：US08975752B2
公开(公告)日：2015-03-10
申请号：US11971492
申请日：2008-01-09
申请人： Alex Chow , R. David Hopkins , Robert J. Drost
发明人： Alex Chow , R. David Hopkins , Robert J. Drost
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/64 , H01L23/00 , H01L25/00 , H04B5/00
CPC分类号： H01L23/5227 , H01L23/48 , H01L23/642 , H01L23/645 , H01L24/06 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2223/6677 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01043 , H01L2924/01051 , H01L2924/01065 , H01L2924/01066 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H04B5/0012 , H04B5/0031 , H04B5/0075 , H04B5/0081
摘要： A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.
摘要翻译：一种多址接近通信系统，其中集成电路芯片上的电气元件将多个信号复用到另一芯片上的单个电接收元件。形成在一个芯片上并接收单独信号的多个焊盘可以电容耦合到另一个芯片上的一个大焊盘。一个芯片上的多个感应线圈可以磁耦合到另一个芯片上的一个大线圈，或者三个或更多个芯片上的感应线圈可用于发送或接收。复用可以基于时间，频率或代码。

76. 发明授权

US08698322B2 Adhesive-bonded substrates in a multi-chip module 有权
标题翻译：多芯片模块中的粘合粘合基板
公开(公告)号：US08698322B2
公开(公告)日：2014-04-15
申请号：US12730823
申请日：2010-03-24
申请人： Robert J. Drost , Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Robert J. Drost , Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/48 , H01L23/5389 , H01L2224/16145 , H01L2224/16225 , H01L2225/06531 , H01L2225/06555 , H01L2924/15153
摘要： A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.
摘要翻译：描述了一种多芯片模块（MCM），其中至少两个基板通过粘合剂层机械耦合，所述粘合剂层在基板的表面上的接近连接器之间保持对准和零（或接近零）的间隔，从而有利于高信号质量基板之间的接近连接。为了提供足够的剪切强度，粘合剂层的厚度大于间隔。这可以使用衬底上的一个或多个正和/或负特征来实现。例如，粘合剂可以结合到：一个表面和在另一个表面下方凹进的通道的内表面; 在两个表面下凹陷的通道的内表面; 或两个表面。在最后一种情况下，零（或接近零）的间距可以通过将接近连接器设置在突出在至少一个衬底表面上的台面上来实现。

77. 发明申请

US20130135017A1 SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY 有权
标题翻译：同步化电路可以解决易变性
公开(公告)号：US20130135017A1
公开(公告)日：2013-05-30
申请号：US13306828
申请日：2011-11-29
申请人： Ian W. Jones , Suwen Yang , Mark R. Greenstreet , Hetal N. Gaywala , Robert J. Drost
发明人： Ian W. Jones , Suwen Yang , Mark R. Greenstreet , Hetal N. Gaywala , Robert J. Drost
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03K3/356173 , H03K3/0375
摘要： The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.
摘要翻译：所公开的实施例提供了一种有助于解决亚稳态问题的同步器锁存电路。该同步器锁存电路包括一组轻负载的交叉耦合晶体管，其形成耦合到两个输出的亚稳分解和状态保持元件。输入同步信号在两个输出之间产生电压差，但不会直接强制输出的状态变化。相反，数据和时钟输入控制晶体管，允许相邻的电源和/或地面网络连接弱影响输出。交叉耦合晶体管然后放大所产生的电压差以产生有效的输出电压，即使在大致相同的时间接收数据输入和时钟信号。因此，同步器锁存电路有助于快速分辨亚稳态并提高同步器性能。

78. 发明授权

US08283766B2 Ramp-stack chip package with static bends 有权
标题翻译：具有静态弯曲的斜面堆叠芯片封装
公开(公告)号：US08283766B2
公开(公告)日：2012-10-09
申请号：US12874446
申请日：2010-09-02
申请人： John A. Harada , David C. Douglas , Robert J. Drost
发明人： John A. Harada , David C. Douglas , Robert J. Drost
IPC分类号： H01L23/52 , H01L23/48 , H01L23/495 , H01L23/02
CPC分类号： H01L25/0657 , G02B6/43 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L29/0657 , H01L2223/54426 , H01L2224/0401 , H01L2224/05555 , H01L2224/10135 , H01L2224/10165 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1601 , H01L2224/16105 , H01L2224/16135 , H01L2224/16151 , H01L2224/1703 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81007 , H01L2224/81141 , H01L2224/81385 , H01L2224/81815 , H01L2224/8185 , H01L2224/819 , H01L2224/8313 , H01L2224/83132 , H01L2224/83193 , H01L2224/8385 , H01L2225/06531 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/014 , H01L2924/1015 , H01L2924/10155 , H01L2924/151
摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.
摘要翻译：描述了斜坡堆叠芯片封装。该芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定具有暴露焊盘的露台。位于大致平行于平台的高带宽斜坡部件被电气和机械耦合到暴露的焊盘。例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部段平行于该方向，并机械耦合到斜坡部件。这些端段可以促进芯片和斜坡部件之间的信号的高带宽通信，例如通过接近通信。

79. 发明授权

US08166644B2 Method for manufacturing an active socket for facilitating proximity communication 有权
标题翻译：用于制造用于促进邻近通信的有源插座的方法
公开(公告)号：US08166644B2
公开(公告)日：2012-05-01
申请号：US12498282
申请日：2009-07-06
申请人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
发明人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
IPC分类号： H05K3/30
CPC分类号： H01L23/48 , H01L25/0652 , H01L2225/06527 , H01L2225/06589 , H01L2924/0002 , H01L2924/3011 , Y10T29/49133 , Y10T29/49169 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.
摘要翻译：本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。该系统还包括集成电路芯片，其具有有源电路和信号焊盘所在的有源面以及与有源面相对的背面。此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠在基板的主动面上。衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。

80. 发明授权

US07994832B2 Aperture generating circuit for a multiplying delay-locked loop 有权
标题翻译：用于倍增延迟锁定环路的光圈产生电路
公开(公告)号：US07994832B2
公开(公告)日：2011-08-09
申请号：US12613936
申请日：2009-11-06
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03L7/00
CPC分类号： H03L7/16 , H03L7/0816
摘要： A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.
摘要翻译：描述了乘法延迟锁定环路（MDLL）。在MDLL中，相位插值器（PI）通过将两个内部信号（其具有不同相位）与来自MDLL中的延迟元件的序列相混合来向选择控制逻辑提供校正信号。该校正信号补偿与选择控制逻辑相关联的延迟，从而确保由选择控制逻辑输出到选择电路（例如多路复用器）的选择脉冲或信号被适当地定时，使得选择电路可以选择性地注入锁定在参考信号中使用边缘的延迟元件的序列。

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