专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5805928A Burst length detection circuit for detecting a burst end time point and generating a burst mode signal without using a conventional burst length detection counter 失效
标题翻译：用于检测突发结束时间点并产生突发模式信号的突发长度检测电路，而不使用传统的突发长度检测计数器
公开(公告)号：US5805928A
公开(公告)日：1998-09-08
申请号：US670842
申请日：1996-06-28
申请人： Jae Jin Lee
发明人： Jae Jin Lee
IPC分类号： G11C11/407 , G11C7/10 , G06F13/28
CPC分类号： G11C7/1021
摘要： A burst length detection circuit comprising at least two registers, each the registers storing a corresponding one of at least two external address signals therein, at least two internal address signal generators, each of the internal address signal generators inputting a corresponding one of the at least two external address signals as its initial value and sequentially incrementing it by one in response to a clock signal to sequentially generate internal address signals, at least two comparators, each of the comparators being operated in response to a control signal to compare an output signal from a corresponding one of the at least two internal address signal generators with an output signal from a corresponding one of the at least two registers, a logic circuit for performing a logic operation with respect to output signals from at least two comparators to detect a burst end time point, and a burst signal generation circuit for generating a burst mode signal with a desired logic value in response to an external burst command signal and a burst end signal from the logic circuit.
摘要翻译：一种突发长度检测电路，包括至少两个寄存器，每个寄存器存储其中至少两个外部地址信号中的相应一个，至少两个内部地址信号发生器，每个内部地址信号发生器输入至少一个对应的一个两个外部地址信号作为其初始值，并且响应于时钟信号顺序地增加一个，以顺序地产生内部地址信号，至少两个比较器，每个比较器响应于控制信号而被操作，以比较来自所述至少两个内部地址信号发生器中的对应的一个内部地址信号发生器具有来自所述至少两个寄存器中对应的一个寄存器的输出信号;逻辑电路，用于相对于来自至少两个比较器的输出信号执行逻辑运算以检测突发结束时间点和用于产生具有期望逻辑v的脉冲串模式信号的脉冲信号发生电路响应于来自逻辑电路的外部脉冲串命令信号和突发结束信号。

72. 发明授权

US5696720A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5696720A
公开(公告)日：1997-12-09
申请号：US777199
申请日：1996-12-27
申请人： Jae Jin Lee
发明人： Jae Jin Lee
IPC分类号： G11C11/34 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1078
摘要： A semiconductor memory device comprising a plurality of memory cells for storing data therein, a data input buffer circuit for buffering an input data signal, a data register circuit for storing the input data signal therein, a switching element for transferring the input data signal to the data register circuit, a register set control logic unit for controlling the switching element, a register set decoding circuit for decoding an output signal from the register set control logic unit and a first address signal, a write data drive circuit for transferring an output data signal from the data input buffer circuit or the data register circuit to a selected one of the memory cells, a first data transfer element for transferring the output data signal from the data input buffer circuit to the write data drive circuit, a second data transfer element for transferring the output data signal from the data register circuit to the write data drive circuit, a data transfer control circuit for generating first and second control signals to control the first and second data transfer element, respectively, and a data register output control circuit for decoding the second control signal from the data transfer control circuit and a second address signal.
摘要翻译：一种半导体存储器件，包括用于存储数据的多个存储单元，用于缓冲输入数据信号的数据输入缓冲电路，用于存储输入数据信号的数据寄存器电路，用于将输入数据信号传送到数据寄存器电路，用于控制开关元件的寄存器组控制逻辑单元，用于对来自寄存器组控制逻辑单元的输出信号进行解码的寄存器组解码电路和第一地址信号，用于传送输出数据信号的写数据驱动电路从所述数据输入缓冲器电路或所述数据寄存器电路到所选存储单元中的一个，用于将所述输出数据信号从所述数据输入缓冲器电路传送到所述写数据驱动电路的第一数据传送元件，用于将输出数据信号从数据寄存器电路传送到写数据驱动电路，用于发生数据传输控制电路分别控制第一和第二数据传送元件的第一和第二控制信号，以及用于从数据传送控制电路解码第二控制信号的数据寄存器输出控制电路和第二地址信号。

73. 发明授权

US09685821B2 Uninterruptable DC power supply providing seamless DC power to load 有权
公开(公告)号：US09685821B2
公开(公告)日：2017-06-20
申请号：US14435532
申请日：2013-10-08
申请人： Jae Jin Lee
发明人： Jae Jin Lee , Kyo Beum Lee
IPC分类号： H02J9/00 , H02J9/06 , H02J7/00
CPC分类号： H02J9/061 , H02J7/0068
摘要： Provided is an uninterruptible direct current (DC) power supply system, which includes a first connection unit electrically connected to a DC power conversion system which converts prevailing AC power into the DC power, a second connection unit which is electrically connected to the load and supplies the DC power to the load, an auxiliary power supply charged by the DC power, and an uninterruptible control unit which supplies the DC power supplied from the DC power conversion system normally connected to the first connection unit to the load through the second connection unit, charges the auxiliary power supply, and controls power to be continuously supplied to the load while perfectly cutting off electrical connection between the DC power conversion system and the auxiliary power supply when the DC power conversion system is disconnected from the first connection unit, is damaged, or short-circuits.

74. 发明授权

US08779797B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08779797B2
公开(公告)日：2014-07-15
申请号：US13544548
申请日：2012-07-09
申请人： Sang Jin Byeon , Jae Jin Lee
发明人： Sang Jin Byeon , Jae Jin Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/173
摘要： A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.
摘要翻译：半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成基本相对应。

75. 发明授权

US08692282B2 Light emitting diode package and light emitting module comprising the same 有权
标题翻译：发光二极管封装和包含该发光二极管封装的发光模块
公开(公告)号：US08692282B2
公开(公告)日：2014-04-08
申请号：US13340867
申请日：2011-12-30
申请人： Byoung Sung Kim , Sang Eun Lim , Jae Jin Lee , Yeoun Chul Son
发明人： Byoung Sung Kim , Sang Eun Lim , Jae Jin Lee , Yeoun Chul Son
IPC分类号： H01L33/00
CPC分类号： H01L33/486 , H01L33/62 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49107 , H05K1/0268 , H05K1/181 , H05K3/3426 , H05K2201/09427 , H05K2201/10106 , Y02P70/613 , H01L2924/00014
摘要： Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal and a second terminal, and in at least one of the first terminal group and the second terminal group, the first terminal is connected to the chip area and the second terminal is separated from the chip area. The first terminal has a first width, the second terminal has a second width, and the first width is different than the second width.
摘要翻译：本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。第一端子组和第二端子组各自包括第一端子和第二端子，并且在第一端子组和第二端子组中的至少一个中，第一端子连接到芯片区域，并且第二端子被分离从芯片区域。第一端子具有第一宽度，第二端子具有第二宽度，并且第一宽度不同于第二宽度。

76. 发明授权

US08520725B2 Data equalizing circuit and data equalizing method 有权
标题翻译：数据均衡电路和数据均衡方法
公开(公告)号：US08520725B2
公开(公告)日：2013-08-27
申请号：US13407546
申请日：2012-02-28
申请人： Chun Seok Jeong , Jae Jin Lee , Chang Sik Yoo , Jang Woo Lee , Seok Joon Kang
发明人： Chun Seok Jeong , Jae Jin Lee , Chang Sik Yoo , Jang Woo Lee , Seok Joon Kang
IPC分类号： H03H7/30
CPC分类号： H04L25/03038
摘要： A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.
摘要翻译：数据均衡电路包括均衡器，其被配置为根据控制码的值控制数据的增益并输出控制器增益; 以及检测单元，被配置为将数据的n个周期分成N个周期，在改变控制码的值的同时，计算n / N个周期的数据转换频率，计算数据的1 / N个周期的数据转换频率的色散值， n / N周期的数据转换频率，最后输出对应于最大色散值的控制码的值，其中n等于或大于2，并且被设置为使得各个n / N周期的边界数据在1 UI数据中具有不同的位置。

77. 发明申请

US20110187408A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：US20110187408A1
公开(公告)日：2011-08-04
申请号：US12836546
申请日：2010-07-14
申请人： Sang Jin Byeon , Jae Jin Lee
发明人： Sang Jin Byeon , Jae Jin Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/173
摘要： A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.
摘要翻译：半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成基本相对应。

78. 发明申请

US20110085601A1 VIDEO DECODING APPARATUS AND METHOD BASED ON MULTIPROCESSOR 审中-公开
标题翻译：基于多处理器的视频解码设备和方法
公开(公告)号：US20110085601A1
公开(公告)日：2011-04-14
申请号：US12836979
申请日：2010-07-15
申请人： Jae Jin Lee , Jun Young Lee , Moo Kyoung Chung , Seong Mo Park , Nak Woong Eum
发明人： Jae Jin Lee , Jun Young Lee , Moo Kyoung Chung , Seong Mo Park , Nak Woong Eum
IPC分类号： H04N7/26
CPC分类号： H04N19/436 , H04N19/44
摘要： Disclosed are a multiprocessor-based video decoding apparatus and method. The multiprocessor-based video decoding apparatus includes: a stream parser dividing an input stream by row and parsing a skip counter and a quantization parameter of the input stream; and a plurality of processors acquiring the plurality of divided streams, the skip counter, and the quantization parameter generated by the stream parser, acquiring decoded information of an upper processor among neighboring processors by row, and parallel-decoding the plurality of divided streams by row. Decoding of an input stream can be parallel-processed by row.
摘要翻译：公开了一种基于多处理器的视频解码装置和方法。基于多处理器的视频解码装置包括：流分析器，其逐行分割输入流，解析跳过计数器和输入流的量化参数; 以及多个处理器，获取多个划分的流，跳过计数器和由流解析器生成的量化参数，通过行获取相邻处理器之间的上位处理器的解码信息，并且按行并行解码多个划分的流。输入流的解码可以由行并行处理。

79. 发明申请

US20110008824A1 DEVICE AND METHOD OF BACTERIA DETECTION 审中-公开
标题翻译：细菌检测的装置和方法
公开(公告)号：US20110008824A1
公开(公告)日：2011-01-13
申请号：US12520253
申请日：2008-08-28
申请人： Jae Jin Lee , Chung Hwan Kim , Min Gun Kim
发明人： Jae Jin Lee , Chung Hwan Kim , Min Gun Kim
IPC分类号： C12Q1/04 , C12M1/42
CPC分类号： G01N33/56911 , C12M41/36
摘要： A bacteria measurement device and method are provided, which separate bacteria from a target object and attach the bacteria to an antibody with fluorescein isothiocyanate applied thereto, generate light using a light emitting unit, and excite the fluorescein isothiocyanate, and in which the excited fluorescein isothiocyanate secondarily emits light, and a light receiving unit receives a light output signal generated through the secondary emission, converts the light output signal into an electrical signal, and converts an analog signal which is the electrical signal into a digital signal, thus measuring the amount and type of bacteria.
摘要翻译：提供了一种细菌测量装置和方法，其将细菌与目标物体分离并将细菌附着于施用有异硫氰酸荧光素的抗体，使用发光单元产生光，并激发异硫氰酸荧光素，并且其中激发的异硫氰酸荧光素二次发光，并且光接收单元接收通过二次发射产生的光输出信号，将光输出信号转换为电信号，并将作为电信号的模拟信号转换为数字信号，从而测量数量和细菌类型

80. 发明授权

US07728369B2 Nonvolatile ferroelectric memory device 有权
公开(公告)号：US07728369B2
公开(公告)日：2010-06-01
申请号：US11717145
申请日：2007-03-13
申请人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
发明人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391 , H01L29/7841
摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式