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    • 74. 发明申请
    • STRAINED SEMICONDUCTOR-ON-INSULATOR BY ADDITION AND REMOVAL OF ATOMS IN A SEMICONDUCTOR-ON-INSULATOR
    • 通过在半导体绝缘体中添加和去除原子的应变半导体绝缘体
    • US20120009766A1
    • 2012-01-12
    • US12830626
    • 2010-07-06
    • Thomas N. AdamStephen W. BedellJoel P. de SouzaKeith E. FogelAlexander ReznicekDevendra K. SadanaGhavam G. Shahidi
    • Thomas N. AdamStephen W. BedellJoel P. de SouzaKeith E. FogelAlexander ReznicekDevendra K. SadanaGhavam G. Shahidi
    • H01L21/20
    • H01L29/1054H01L29/7833
    • A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.
    • 提供了一种形成不包括晶片接合的应变绝缘体上半导体(SSOI)衬底的方法。 在本公开中,在绝缘体上硅(SOI)衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中,松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸,因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸, 下层SOI层的平面晶格参数。 在另一实施例中,松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸,因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸, 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后,从该层去除松弛和掺杂硅层内的掺杂剂,将松散和掺杂的硅层转化成形成在上层的应变(压缩或拉伸)硅层 SOI衬底的表面。
    • 78. 发明授权
    • High-quality SGOI by annealing near the alloy melting point
    • 高品质SGOI通过在合金熔点附近退火
    • US07348253B2
    • 2008-03-25
    • US10855915
    • 2004-05-27
    • Stephen W. BedellHuajie ChenAnthony G. DomenicucciKeith E. FogelRichard J. MurphyDevendra K. Sadana
    • Stephen W. BedellHuajie ChenAnthony G. DomenicucciKeith E. FogelRichard J. MurphyDevendra K. Sadana
    • H01L21/84
    • H01L21/26506H01L21/324H01L21/7624H01L21/76254H01L29/1054
    • A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
    • 提供一种形成低缺陷,基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤,并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散,从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外,由于加热步骤在接近最终SiGe合金的熔点的温度下进行,所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中,加热步骤包括氧化过程,其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。