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71. 发明授权

US07759239B1 Method of reducing a critical dimension of a semiconductor device 有权
标题翻译：降低半导体器件临界尺寸的方法
公开(公告)号：US07759239B1
公开(公告)日：2010-07-20
申请号：US12435552
申请日：2009-05-05
申请人： Yu Chao Lin , De-Fang Chen , Chia-Wei Chang , Yih-Ann Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Cheng
发明人： Yu Chao Lin , De-Fang Chen , Chia-Wei Chang , Yih-Ann Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Cheng
IPC分类号： H01L21/3205
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极层，在栅极层上形成硬掩模层，在硬掩模层上形成第一材料层，形成在第一材料层上具有开口的图案化光刻胶层，蚀刻第一材料层，其包括在半导体器件上形成第二材料层并蚀刻第一和第二材料层，重复该循环，直到硬掩模层通过减小的开口暴露，在最后一个循环中形成的减小的开口，蚀刻硬掩模层以暴露栅极层，并且使用硬掩模层图案化栅极层。第一和第二材料层的蚀刻选择性小于第二材料层和光致抗蚀剂层的蚀刻选择性。

72. 发明申请

US20100068861A1 METHOD OF DEFINING GATE STRUCTURE HEIGHT FOR SEMICONDUCTOR DEVICES 有权
标题翻译：定义半导体器件的门结构高度的方法
公开(公告)号：US20100068861A1
公开(公告)日：2010-03-18
申请号：US12339483
申请日：2008-12-19
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
IPC分类号： H01L21/8234 , H01L21/28
CPC分类号： H01L29/7848 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L29/165 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/66636
摘要： Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.
摘要翻译：提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。该方法包括在衬底上形成覆盖层并覆盖栅极结构。将涂层回蚀刻以露出栅极结构的一部分。蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

73. 发明授权

US07511349B2 Contact or via hole structure with enlarged bottom critical dimension 有权
标题翻译：接触或通孔结构，扩大底部临界尺寸
公开(公告)号：US07511349B2
公开(公告)日：2009-03-31
申请号：US11207450
申请日：2005-08-19
申请人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
发明人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76897 , H01L21/76804 , H01L23/485 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.
摘要翻译：集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。缓冲层位于底层之上。电介质层在缓冲层之上。孔形成并延伸穿过介电层和缓冲层，并向下层开放。该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。保形阻挡层覆盖孔中的介电层和缓冲层的表面。孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

74. 发明授权

US07186662B2 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US07186662B2
公开(公告)日：2007-03-06
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L21/461
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

75. 发明授权

US06790770B2 Method for preventing photoresist poisoning 有权
标题翻译：防止光致抗蚀剂中毒的方法
公开(公告)号：US06790770B2
公开(公告)日：2004-09-14
申请号：US10035690
申请日：2001-11-08
申请人： Chao-Cheng Chen , Jen-Cheng Liu , Jyu-Horng Shieh
发明人： Chao-Cheng Chen , Jen-Cheng Liu , Jyu-Horng Shieh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.
摘要翻译：如果提供用于通过在通孔开口中形成树脂塞以改善来自低k IMD层的含氮物质的扩散的方法，以在随后的平版印刷图案化和RIE蚀刻工艺中形成二维镶嵌工艺中的光刻图案化方法沟槽开口基本上形成在通孔开口上方。

76. 发明授权

US06323121B1 Fully dry post-via-etch cleaning method for a damascene process 有权
标题翻译：用于镶嵌工艺的完全干燥的经过蚀刻的清洁方法
公开(公告)号：US06323121B1
公开(公告)日：2001-11-27
申请号：US09570018
申请日：2000-05-12
申请人： Jen-Cheng Liu , Chao-Cheng Chen , Li-Chih Chao , Chia-Shiung Tsai , Ming-Huei Lui
发明人： Jen-Cheng Liu , Chao-Cheng Chen , Li-Chih Chao , Chia-Shiung Tsai , Ming-Huei Lui
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76807
摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.
摘要翻译：描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

77. 发明授权

US6133145A Method to increase the etch rate selectivity between metal and photoresist via use of a plasma treatment 有权
标题翻译：通过使用等离子体处理来增加金属和光致抗蚀剂之间的蚀刻速率选择性的方法
公开(公告)号：US6133145A
公开(公告)日：2000-10-17
申请号：US169434
申请日：1998-10-09
申请人： Chao-Cheng Chen
发明人： Chao-Cheng Chen
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0273 , H01L21/76838
摘要： A process for fabricating an aluminum based interconnect structure, using a plasma treated photoresist shape as an etch mask, has been developed. The process features treating a photoresist shape, to be used as an etch mask during RIE patterning procedures, in a nitrogen containing plasma. The plasma nitrogen treated photoresist shape is eroded at a decreased rate, when compared to counterpart non-treated photoresist shapes, during the RIE procedure used to fabricate the aluminum based interconnect structure. The increased etch rate ratio, between layers used for the interconnect structure, and the plasma treated photoresist shape, allows thinner photoresist shapes to be used, and therefore allows narrower lines and spaces to be achieved.
摘要翻译：已经开发了使用等离子体处理的光致抗蚀剂形状作为蚀刻掩模来制造铝基互连结构的方法。该方法的特征是在含氮等离子体中处理光刻胶形状，以在RIE图案化步骤期间用作蚀刻掩模。在用于制造铝基互连结构的RIE程序期间，与对照未处理的光致抗蚀剂形状相比，等离子体氮处理的光致抗蚀剂形状以降低的速率被侵蚀。用于互连结构的层之间的增加的蚀刻速率比和等离子体处理的光致抗蚀剂形状允许使用更薄的光致抗蚀剂形状，因此允许实现更窄的线和空间。

78. 发明授权

US5989784A Etch recipe for embedded DRAM passivation with etch stopping layer scheme 失效
标题翻译：用蚀刻停止层方案的嵌入式DRAM钝化蚀刻配方
公开(公告)号：US5989784A
公开(公告)日：1999-11-23
申请号：US55463
申请日：1998-04-06
申请人： Yu-Hua Lee , Cheng-Ming Wu , Chao-Cheng Chen
发明人： Yu-Hua Lee , Cheng-Ming Wu , Chao-Cheng Chen
IPC分类号： H01L21/768 , H01L23/525 , G03F7/40 , B44C1/22 , C03C15/00 , C25F3/00
CPC分类号： H01L23/5258 , H01L21/76802 , H01L2924/0002
摘要： A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.
摘要翻译：使用专门的2级蚀刻工艺在保险丝开口（或窗口）92中的熔丝16上方形成蚀刻停止层40的方法。本发明具有两个重要特征：首先，蚀刻停止层40由用于在基板上制造半导体器件的多晶硅层（P2或P4）形成。蚀刻停止层40优选由多晶硅层形成，用于从接触到衬底10（P2）或形成电容器（P4）的一部分。第二，使用专门的两级蚀刻工艺，其中第二阶段蚀刻蚀刻停止层40，同时在金属焊盘85上形成钝化层114.该方法包括：在保险丝区域15上方的所述隔离区域10上形成保险丝16 ; 形成覆盖保险丝16的第一电介质层30; 在第一介电层30上形成蚀刻停止层40; 在所述蚀刻停止层上形成绝缘层43; 在绝缘层43中通过在第一蚀刻阶段中蚀刻完整的熔融光致抗蚀剂开口90A并停止蚀刻停止层40上的第一蚀刻阶段来在绝缘层43中形成熔丝开口92; 并且在第二蚀刻阶段通过熔丝开口92中的蚀刻停止层40进行蚀刻。

79. 发明授权

US5942446A Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer 失效
标题翻译：用于形成图案化含硅介电层的氟碳聚合物层沉积主要预蚀刻等离子体蚀刻方法
公开(公告)号：US5942446A
公开(公告)日：1999-08-24
申请号：US928235
申请日：1997-09-12
申请人： Chao-Cheng Chen , Chen-Hua Yu
发明人： Chao-Cheng Chen , Chen-Hua Yu
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76802
摘要： A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer. The second plasma etch method employs a second etchant gas composition comprising a second fluoro etchant gas which predominantly etches the partially etched silicon containing dielectric layer in forming the patterned silicon containing dielectric layer.
摘要翻译：一种用于在微电子制造中形成图案化含硅介电层的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成含硅介电层。然后在含硅电介质层上形成硬掩模层，其中硬掩模层离开暴露一部分含硅电介质层。然后通过第一等离子体蚀刻方法将含硅介电层部分地蚀刻以形成部分蚀刻的含硅介电层。第一等离子体蚀刻方法采用第一蚀刻剂气体组合物，其包括在至少硬掩模层上主要形成含氟聚合物层的第一碳氟化合物蚀刻剂气体。最后，然后通过第二等离子体蚀刻方法蚀刻部分蚀刻的含硅介电层，以形成图案化的含硅介电层。第二等离子体蚀刻方法采用包含第二氟蚀刻剂气体的第二蚀刻剂气体组合物，其主要在形成图案化的含硅介电层时蚀刻部分蚀刻的含硅介电层。

80. 发明授权

US5807789A Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) 失效
标题翻译：用于形成具有锥形轮廓和圆角的浅沟槽的方法用于应用浅沟槽隔离（STI）
公开(公告)号：US5807789A
公开(公告)日：1998-09-15
申请号：US821353
申请日：1997-03-20
申请人： Chao-Cheng Chen , C. S. Tsai , C. H. Yu
发明人： Chao-Cheng Chen , C. S. Tsai , C. H. Yu
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3065 , H01L21/76232 , Y10S438/978
摘要： The present invention is a method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI). This invention utilizes a multiple-step dry etching process with reduced RF power and increased pressure to etch a shallow trench. This takes advantage of different degree of polymer deposition in different steps by varing the pressure and the RF power. Thus, a shallow trench with tapered profile and round corners is achieved.
摘要翻译：本发明是用于形成具有锥形轮廓和圆角的浅沟槽的方法，用于应用浅沟槽隔离（STI）。本发明利用具有降低的RF功率和增加的压力来蚀刻浅沟槽的多级干蚀刻工艺。这通过改变压力和RF功率在不同步骤中利用不同程度的聚合物沉积。因此，实现了具有锥形轮廓和圆角的浅沟槽。

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