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    • 71. 发明授权
    • Memory system employing pipeline process for accessing memory banks
    • 采用流水线处理存储器的存储器系统
    • US5586282A
    • 1996-12-17
    • US340312
    • 1994-11-14
    • Hideyuki IinoHiromasa Takahashi
    • Hideyuki IinoHiromasa Takahashi
    • G06F12/06G06F13/42
    • G06F12/0607G06F12/06G06F13/4243
    • A memory access system employs a pipe-line process in which access can be carried out for a microprocessor using one cycle of two clocks and for a microprocessor using one cycle of one clock. Access speed of a main memory can be considerably improved ensuring applicability in general use. A transition request signal to a pipe-line is received, a control signal that continues as long as the cycle number corresponding to at least the address first-out number of the pipe-line immediately after the start of the pipe-line operation is produced. Concurrently, a data complete signal indicating the completion of data access for a bank is produced during the time that either of the above two signals is also generating an address latch signal synchronized to a clock signal and routed to respective banks, for executing high speed data access.
    • 存储器访问系统采用管线处理,其中可以对使用两个时钟的一个周期的微处理器以及使用一个时钟的一个周期的微处理器执行访问。 可以大大提高主存储器的访问速度,确保在一般使用中的适用性。 接收到管线的转换请求信号,产生一个控制信号,只要产生与管线运行开始之后的至少管道地址先出号码对应的循环数, 。 同时,在上述两个信号之一也产生与时钟信号同步的地址锁存信号并被路由到各个存储体的时间期间产生指示存储体的数据访问完成的数据完成信号,以执行高速数据 访问。
    • 72. 发明授权
    • Virtual memory address translation apparatus and method using link,
auxiliary link and page tables
    • 虚拟内存地址转换装置和方法使用链接,辅助链接和页表
    • US5584005A
    • 1996-12-10
    • US123474
    • 1993-09-20
    • Hitoshi MiyaokuHiromasa Takahashi
    • Hitoshi MiyaokuHiromasa Takahashi
    • G06F12/10G06F12/02
    • G06F12/0292
    • In a method and apparatus for address translation for translating a 64-bit virtual address into a real address, the 64-bit virtual address comprises a segment number, a page index and a page offset. When this virtual address is translated into a real address, high order bits of the segment number are first input to a hash generation circuit to obtain a hash address of a link table, and this link table is retrieved by an address obtained by adding lower order bits of the segment number as an offset to obtain tag information of the virtual address and a base address of a page table. Next, the tag information of the virtual address obtained in this manner is compared with the original segment number, and the base address of the page table is judged as correct when they coincide with each other. The page table is retrieved by an address obtained by adding a page index as an offset to this base address to obtain a page frame number, and the real address is obtained by combining the original page offset with the page frame number. According to this construction, address translation can be carried out at a higher speed while maintaining compatibility with the 32-bit virtual address.
    • 在用于将64位虚拟地址转换为实际地址的地址转换的方法和装置中,64位虚拟地址包括段号,页索引和页偏移。 当该虚拟地址被转换为实际地址时,首先将片段编号的高位进行输入到散列生成电路以获得链接表的散列地址,并且通过将较低次序 分段号的比特作为偏移量,以获得虚拟地址的标签信息和页表的基地址。 接下来,将以这种方式获得的虚拟地址的标签信息与原始段号进行比较,并且当它们彼此一致时,判断页表的基址是正确的。 通过将页索引作为偏移量添加到该基地址而获得的地址来获取页表,以获得页框号,并且通过将原始页偏移量与页框号组合来获得实地址。 根据这种结构,可以以更高的速度进行地址转换,同时保持与32位虚拟地址的兼容性。
    • 73. 发明授权
    • Magnetic head and magnetic recording apparatus
    • 磁头和磁记录装置
    • US08238064B2
    • 2012-08-07
    • US12315525
    • 2008-12-03
    • Masaki YamadaHiromasa Takahashi
    • Masaki YamadaHiromasa Takahashi
    • G11B5/10G11B5/33
    • G11B5/332B82Y25/00G01R33/093G01R33/1284G11B5/3909
    • Embodiments of the present invention provide an accumulation element with high resolving power and high output suitable for magnetic recording and reproducing at high recording density. According to one embodiment, a plurality of spin injection parts and are provided to increase the total amount of spin electrons. The spin accumulation element is composed of a non-magnetic conductor, a first magnetic conductor, a second magnetic conductor, and a third magnetic conductor, each of which are in contact with the non-magnetic conductor through the tunneling junction. An output voltage due to the spin accumulation effect is detected as a potential difference between the non-magnetic conductor and the third magnetic conductor. The first magnetic conductor of the first spin injection part is fixed by a first antiferromagnetic conductor and the second magnetic conductor of the second spin injection part is fixed by a second antiferromagnetic conductor so that their directions of magnetization are anti-parallel to each other.
    • 本发明的实施例提供了一种具有高分辨率和高输出的累积元件,其适用于在高记录密度下的磁记录和再现。 根据一个实施例,提供多个自旋注入部分并且被提供以增加自旋电子的总量。 自旋累积元件由非磁性导体,第一磁性导体,第二磁性导体和第三磁性导体组成,它们都通过隧道结与非磁性导体接触。 检测由于自旋累积效应引起的输出电压作为非磁性导体和第三磁性导体之间的电位差。 第一自旋注入部分的第一磁性导体由第一反铁磁导体固定,第二自旋注入部分的第二磁性导体由第二反铁磁导体固定,使得它们的磁化方向彼此反平行。
    • 74. 发明申请
    • VECTOR PROCESSING CIRCUIT, COMMAND ISSUANCE CONTROL METHOD, AND PROCESSOR SYSTEM
    • 矢量处理电路,指令发布控制方法和处理器系统
    • US20120124332A1
    • 2012-05-17
    • US13279482
    • 2011-10-24
    • GE YiYoshimasa TakebeHiromasa Takahashi
    • GE YiYoshimasa TakebeHiromasa Takahashi
    • G06F9/302G06F9/44
    • G06F9/30014G06F9/30109G06F9/30149G06F9/3836
    • A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
    • 矢量处理电路包括包括多个阵列元素的矢量寄存器文件,命令发布控制电路和多个流水线运算单元。 每个流水线运算单元通过多个周期以部分方式,通过一个命令对存储在源表示的数组元素中的数据进行算术处理,并将该结果存储在通过多个周期的一个命令作为目的地表示的数组元素中。 当前一个命令的数据字长度大于后续命令的数据字长时,命令发布控制电路根据命令的数据字长度改变数组元素的数据大小,并确定数组元素与 在前一个命令的非头循环处理,以及要在后续命令的头循环处理的数组元素。
    • 75. 发明申请
    • MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY USING SAME
    • MAGNETORESISTANCE效应元件和磁记忆体单元和磁性随机存取存储器
    • US20110233700A1
    • 2011-09-29
    • US13133177
    • 2009-11-16
    • Jun HayakawaHiromasa Takahashi
    • Jun HayakawaHiromasa Takahashi
    • H01L29/82
    • H01L27/228B82Y25/00H01F10/16H01F10/3254H01F10/3272H01L43/08
    • Disclosed are a magnetoresistance effect element equipped with an magnesium oxide passivation layer, and a high-speed, ultra-low power consumption nonvolatile memory using said element. A tunnel magnetoresistance effect (TMR) film comprised of a ferromagnetic free layer, an insulation layer, and a ferromagnetic fixed layer is provided, and an MgO passivation layer is provided on the side walls of a protective layer and an orientation control layer, thus suppressing elemental diffusion of a tunnel magnetoresistance effect (TMR) element from each layer due to thermal processing at 350° or higher and obtaining a magnetic memory cell and magnetic random access memory having stable, high-output reading and a low current writing characteristics. Furthermore, when CoFeB is used in the ferromagnetic layer and MgO is used in the insulation layer, it is preferable that the MgO passivation layer have an (001) orientation.
    • 公开了配备有氧化镁钝化层的磁阻效应元件和使用所述元件的高速,超低功耗的非易失性存储器。 提供了由铁磁性自由层,绝缘层和强磁性固定层构成的隧道磁阻效应(TMR)膜,并且在保护层和取向控制层的侧壁上设置MgO钝化层,从而抑制 由于350°以上的热处理,每层的隧道磁阻效应(TMR)元件的元素扩散,并获得具有稳定的高输出读数和低电流写入特性的磁存储单元和磁随机存取存储器。 此外,当在铁磁层中使用CoFeB并且在绝缘层中使用MgO时,优选MgO钝化层具有(001)取向。
    • 77. 发明申请
    • Magnetic read head and magnetic read write system
    • 磁读头和磁读写系统
    • US20080176107A1
    • 2008-07-24
    • US11984377
    • 2007-11-16
    • Hiromasa TakahashiMasaki Yamada
    • Hiromasa TakahashiMasaki Yamada
    • G11B5/33
    • G11B5/3903G11B5/398Y10T428/11
    • To provide a magnetic head that is suited for high recording density magnetic read and write, and has little noise. A magnetic pinned layer is formed on a non-magnetic electrode layer via a first insulating layer, and a magnetic free layer is formed on a medium-side plane of the non-magnetic electrode layer via a second insulating layer. A circuit for flowing current between the non-magnetic electrode layer and the magnetic pinned layer via the first insulating layer, and a circuit for measuring voltage between the non-magnetic electrode layer and the magnetic free layer are connected to the magnetic free layer. The medium-side plane on which the magnetic free layer is formed may be a plane substantially parallel to the surface of the medium, or may be a plane tilted from the surface of the medium.
    • 提供适合高记录密度磁读写的磁头,噪音小。 经由第一绝缘层在非磁性电极层上形成磁性被钉扎层,经由第二绝缘层在非磁性电极层的中间侧平面上形成无磁性层。 用于经由第一绝缘层在非磁性电极层和磁性被钉扎层之间流动电流的电路和用于测量非磁性电极层和无磁性层之间的电压的电路连接到无磁性层。 形成有磁性层的中间平面可以是基本上平行于介质表面的平面,也可以是从介质表面倾斜的平面。
    • 79. 发明申请
    • Magnetic head and magnetic recording/reproducing device
    • 磁头和磁记录/再现装置
    • US20050088787A1
    • 2005-04-28
    • US10931038
    • 2004-09-01
    • Hiromasa TakahashiKonchi Ito
    • Hiromasa TakahashiKonchi Ito
    • G11B5/127G11B5/33G11B5/39H01F10/16H01F10/32H01L43/08
    • B82Y25/00B82Y10/00G11B5/3906G11B2005/3996
    • A magnetic head includes a first electrode layer, a first ferromagnetic electrode pair that is electrically connected to the first electrode layer, and a second ferromagnetic electrode pair that intersects with a current which flows between the first ferromagnetic electrode pairs and is electrically connected with the first electrode layer. The current is allowed to flow between the first ferromagnetic electrode pair through the first electrode layer to accumulate spin electrons in the first electrode layer. A direction of magnetization of the fourth ferromagnetic electrode layer changes upon application of an external magnetic field. The second ferromagnetic electrode pair is so arranged as to intersect with the current that flows between the first ferromagnetic electrode pair, to increase a rate of change in the output signal of the in-plane spin accumulation effect.
    • 磁头包括第一电极层,电连接到第一电极层的第一铁磁电极对和与在第一铁磁电极对之间流动并与第一电磁体电连接的电流相交的第二铁磁电极对 电极层。 允许电流通过第一电极层在第一铁磁电极对之间流动,以在第一电极层中积累自旋电子。 第四铁磁性电极层的磁化方向在施加外部磁场时发生变化。 第二铁磁电极对被布置为与在第一铁磁电极对之间流动的电流相交,以增加平面内自旋累积效应的输出信号的变化率。