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71. 发明申请

US20100317158A1 Method for Forming Nanotube Semiconductor Devices 有权
标题翻译：形成纳米管半导体器件的方法
公开(公告)号：US20100317158A1
公开(公告)日：2010-12-16
申请号：US12484166
申请日：2009-06-12
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L21/336 , H01L21/331 , H01L21/329
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0692 , H01L29/1095 , H01L29/6609 , H01L29/66143 , H01L29/66348 , H01L29/66666 , H01L29/7397 , H01L29/861 , H01L29/872
摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
摘要翻译：形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。薄的外延层具有均匀的掺杂浓度。在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。第一和第二外延层具有均匀的掺杂浓度。选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。在一个实施例中，半导体本体是轻掺杂的P型衬底。可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

72. 发明申请

US20100314659A1 Nanotube Semiconductor Devices 有权
标题翻译：纳米管半导体器件
公开(公告)号：US20100314659A1
公开(公告)日：2010-12-16
申请号：US12484170
申请日：2009-06-12
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/0886 , H01L21/26586 , H01L27/0623 , H01L27/0629 , H01L27/0664 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0676 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/36 , H01L29/365 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/41775 , H01L29/4236 , H01L29/42368 , H01L29/66136 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/8613 , H01L29/872 , H01L29/8725
摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.
摘要翻译：半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层其中第二外延层电连接到第二半导体层。第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度选择平均掺杂浓度以在操作中实现电荷平衡。

73. 发明申请

US20100190307A1 HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
标题翻译：高密度TRENCH MOSFET，具有单面罩预定门和接触孔
公开(公告)号：US20100190307A1
公开(公告)日：2010-07-29
申请号：US12362414
申请日：2009-01-29
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽，并且在栅极沟槽处具有比那些沟槽更宽的开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

74. 发明授权

US07709336B2 Metal hard mask method and structure for strained silicon MOS transistors 有权
标题翻译：应变硅MOS晶体管的金属硬掩模方法和结构
公开(公告)号：US07709336B2
公开(公告)日：2010-05-04
申请号：US11321767
申请日：2005-12-28
申请人： Xian J. Ning , Hanming Wu , John Chen
发明人： Xian J. Ning , Hanming Wu , John Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/32139 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.
摘要翻译：半导体集成电路器件。该器件具有覆盖半导体衬底的半导体衬底和电介质层。该装置还具有包括边缘的门结构。金属硬掩模层覆盖栅极结构。电介质层在门结构的边缘上形成侧墙，以保护包括边缘的栅结构。金属硬掩模层的暴露部分覆盖栅极结构。在蚀刻源区域和蚀刻漏极区域中提供硅锗填充材料。蚀刻的源极区域和蚀刻的漏极区域各自耦合到栅极结构。该器件在至少形成在蚀刻源极区域和蚀刻漏极区域中的硅锗材料之间具有在填充源极区域和填充的漏极区域之间的应变通道区域。电连接耦合到覆盖栅极结构的金属硬掩模。可选地，该装置具有覆盖金属硬掩模的第二金属层。

75. 发明授权

US07494593B1 Method for forming a cantilever and tip 失效
标题翻译：形成悬臂和尖端的方法
公开(公告)号：US07494593B1
公开(公告)日：2009-02-24
申请号：US10879971
申请日：2004-06-28
申请人： Chien-Hua Chen , John Chen , Sriram Ramamoorthi
发明人： Chien-Hua Chen , John Chen , Sriram Ramamoorthi
IPC分类号： C25F3/12
CPC分类号： B81C1/0015 , B81B2201/07
摘要： A method is disclosed for forming a single crystal cantilever and tip on a substrate. The method can include the operation of defining an implant area on the substrate with a layer of photoresist. A further operation can be implanting oxygen into the substrate in the implant area to a predetermined depth to form a buried oxide layer. The buried oxide layer can define a bottom of the single crystal cantilever and tip. Another operation can involve shaping the single crystal cantilever and tip from the substrate above the buried oxide layer.
摘要翻译：公开了一种用于在基板上形成单晶悬臂和尖端的方法。该方法可以包括在衬底上用光致抗蚀剂层限定植入区域的操作。进一步的操作可以是将植入区域中的氧注入到预定深度的衬底中以形成掩埋氧化物层。掩埋氧化物层可以限定单晶悬臂和尖端的底部。另外的操作可以包括从掩埋氧化物层上方的衬底上形成单晶悬臂和尖端。

76. 外观设计

USD579326S1 Fruit container 有权
公开(公告)号：USD579326S1
公开(公告)日：2008-10-28
申请号：US29286157
申请日：2007-04-25
申请人： John Chen
设计人： John Chen

77. 发明申请

US20080173941A1 ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS 审中-公开
标题翻译：用于应变硅MOS晶体管的后续外延生长的硅蚀刻蚀刻方法和结构
公开(公告)号：US20080173941A1
公开(公告)日：2008-07-24
申请号：US11678582
申请日：2007-02-24
申请人： Bei Zhu , Paolo Bonfanti , Hanming Wu , Da Wei Gao , John Chen
发明人： Bei Zhu , Paolo Bonfanti , Hanming Wu , Da Wei Gao , John Chen
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.
摘要翻译：一种半导体集成电路器件，包括半导体衬底，例如硅晶片，绝缘体上硅。该器件具有覆盖半导体衬底的电介质层和覆盖该介电层的栅极结构。器件还在栅极结构附近的半导体衬底的一部分内部具有通道区域，以及半导体衬底中的轻掺杂源极/漏极区域，以从栅极结构的部分下方的扩散袋区域。该装置在栅极结构的边缘上具有侧壁间隔物。该器件还具有蚀刻源极区和蚀刻漏极区。第一源极区域和第一漏极区域中的每一个的特征在于具有基本上垂直的壁的凹陷区域，底部区域和将垂直壁连接到底部区域的圆角区域。

78. 发明申请

US20080119032A1 ETCHING METHOD AND STRUCTURE USING A HARD MASK FOR STRAINED SILICON MOS TRANSISTORS 有权
标题翻译：使用用于应变硅MOS晶体管的硬掩模的蚀刻方法和结构
公开(公告)号：US20080119032A1
公开(公告)日：2008-05-22
申请号：US11609748
申请日：2006-12-12
申请人： John Chen , Hanming Wu , Da Wei Gao , Bei Zhu , Paolo Bonfanti
发明人： John Chen , Hanming Wu , Da Wei Gao , Bei Zhu , Paolo Bonfanti
IPC分类号： H01L21/3205
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , Y10S438/938
摘要： A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.
摘要翻译：一种形成应变硅集成电路器件的方法。该方法包括提供半导体衬底并形成覆盖半导体衬底的电介质层。该方法还包括形成覆盖在电介质层上的栅极层，并形成覆盖栅极层的硬掩模。该方法使栅极层形成包括使用硬掩模的边缘作为保护层的栅极结构。该方法形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。该方法从电介质层形成间隔物，同时保持覆盖栅极结构的硬掩模。该方法使用电介质层和硬掩模作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域，同时硬掩模防止栅极结构的任何部分暴露。在优选实施例中，该方法保持覆盖栅极结构的硬掩模。该方法包括将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域，同时保持栅极层的任何部分不被使用硬掩模曝光，使得栅极结构基本上是空的来自硅锗材料的任何永久性沉积，其使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。在优选实施例中，该方法从栅极结构去除硬掩模以露出栅极结构的顶部并且保持栅极结构的顶部基本上不含任何硅锗材料。

79. 发明申请

US20080114197A1 Wet Scrubbing and Recycle of Effluent-Contaminating Catalyst Particles in an Oxygenate-to-Olefin Process 审中-公开
标题翻译：污水 - 污染催化剂颗粒在氧化烯 - 烯烃工艺中的湿法洗涤和回收
公开(公告)号：US20080114197A1
公开(公告)日：2008-05-15
申请号：US12014400
申请日：2008-01-15
申请人： Bradford Bjorklund , John Chen
发明人： Bradford Bjorklund , John Chen
IPC分类号： C07C1/26
CPC分类号： C07C1/20 , C07C2529/85 , C10G3/49 , C10G3/57 , C10G2300/4081 , C10G2300/805 , C10G2400/20 , Y02P20/584 , Y02P30/20 , Y02P30/42 , C07C11/02
摘要： The economics of a catalytic process using a fluidized conversion zone and a relatively expensive catalyst for converting an oxygenate to light olefins are substantially improved by recovering and recycling effluent contaminating catalyst particles from the product effluent stream withdrawn from the conversion zone which are present despite the use of one or more vapor-solid cyclone separating means to clean up this effluent stream. The contaminating catalyst particles are separated from this product effluent stream using a wet scrubbing zone and an optional dewatering zone to recover a slurry containing the contaminated particles which, quite surprisingly, can be successfully directly recycled to the oxygenate conversion zone or to the associated catalyst regeneration zone without loss of any substantial amount of catalytic activity thereby decreasing the amount of fresh catalyst addition required to make up for this source of catalyst loss.
摘要翻译：使用流化转化区的催化方法的经济性和用于将含氧化合物转化成轻质烯烃的相对昂贵的催化剂的经济性通过回收和再循环流出物污染的催化剂颗粒而得到显着改善，所述流出物污染的催化剂颗粒从转化区提取的产物流出物流中，的一种或多种蒸汽 - 固体旋风分离装置，以清理该流出物流。使用湿式洗涤区和任选的脱水区将污染的催化剂颗粒与该产物流出物流分离，以回收含有污染颗粒的浆料，这相当令人惊奇地可以成功地直接再循环到含氧化合物转化区或相关联的催化剂再生区，而不会损失任何相当大量的催化活性，从而减少了弥补该催化剂损失源所需的新鲜催化剂添加量。

80. 发明申请

US20080090583A1 RESOURCE ALLOCATION, SCHEDULING, AND SIGNALING FOR GROUPING REAL TIME SERVICES 有权
标题翻译：资源分配，调度和信号分组实时服务
公开(公告)号：US20080090583A1
公开(公告)日：2008-04-17
申请号：US11840534
申请日：2007-08-17
申请人： Jin Wang , Arty Chandra , John Chen , Mohammed Sammour , Stephen Terry
发明人： Jin Wang , Arty Chandra , John Chen , Mohammed Sammour , Stephen Terry
IPC分类号： H04Q7/20 , H04M1/00 , H04Q7/00
CPC分类号： H04W72/121 , H04W72/042 , H04W72/1231 , H04W72/1289
摘要： The present invention is a method and apparatus for resource allocation signaling for grouping user real time services. Uplink signaling for voice activity reporting of each user's transition between an active state and an inactive voice state is sent from a wireless transmit/receive unit to a Node B. Radio resource allocation to users of a wireless communication system varies based on user measurement reporting, a pre-determined pattern such as frequency hopping, or a pseudorandom function. Grouping methods are adjusted to better utilize the voice activity factor, so that statistical multiplexing can be used to more efficiently utilize physical resources.
摘要翻译：本发明是用于分组用户实时业务的资源分配信令的方法和装置。从无线发射/接收单元向节点B发送用于每个用户在活动状态和非活动语音状态之间的转换的语音活动报告的上行链路信令。根据用户测量报告，无线资源分配给无线通信系统的用户，诸如跳频或伪随机功能的预定模式。调整分组方法以更好地利用语音活动因素，使得可以使用统计复用来更有效地利用物理资源。

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