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71. 发明授权

US07529130B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07529130B2
公开(公告)日：2009-05-05
申请号：US11389252
申请日：2006-03-27
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/0483 , G11C16/28 , G11C2211/5631 , G11C2211/5634
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M≧2) physical quantity levels is written, and at least one reference cell, in which a reference physical quantity level is written, are defined in the memory cell array, and the sense amplifier circuit detects a cell current difference between the information cell and the reference cell selected simultaneously in the memory cell array to sense data defined by the M physical quantity levels of the information cell.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 以及读出放大器电路，被配置为读出存储单元阵列的数据，其中写入了M（M> = 2）个物理量级别中的一个的多个信息单元和至少一个参考单元，在存储单元阵列中定义参考物理量级别，并且读出放大器电路检测在存储单元阵列中同时选择的信息单元和参考单元之间的单元电流差，以感测由M个物理信息单元的数量级别。

72. 发明授权

US07495965B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07495965B2
公开(公告)日：2009-02-24
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联在VRDEC和TG之间的PMOS晶体管P2和高压NMOS晶体管D3; 串联在VRDEC和NA之间的PMOS晶体管P1和高电压NMOS晶体管D2; 串联在TG和Vss之间的NMOS晶体管N2和高电压NMOS晶体管D6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N1和高电压NMOS晶体管D5由解码输出Aa驱动。 P1和P2的门和排水管交叉耦合。 D3和D2的门分别耦合到TG和NA。

73. 发明授权

US07394680B2 Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode 有权
标题翻译：具有记录层电极的可变电阻元件的电阻变化存储器件在写入或擦除模式下用作阳离子源
公开(公告)号：US07394680B2
公开(公告)日：2008-07-01
申请号：US11761391
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0042 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate to have a stack structure of a variable resistance element and an access element, the variable resistance element storing a high resistance state or a low resistance state in a non-volatile manner, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate, wherein the variable resistance element includes: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 至少一个单元阵列形成在所述半导体衬底上方以具有可变电阻元件和存取元件的堆叠结构，所述可变电阻元件以非易失性方式存储高电阻状态或低电阻状态，所述存取元件具有在选择状态下为十倍以上的一定电压范围内的截止电阻值; 以及形成在所述半导体基板上的读/写电路，其中所述可变电阻元件包括：由包含至少一个过渡元件的复合化合物和用于容纳阳离子离子的空腔位置形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在腔部位中的记录层。

74. 发明申请

US20070285966A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285966A1
公开(公告)日：2007-12-13
申请号：US11761391
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0042 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate to have a stack structure of a variable resistance element and an access element, the variable resistance element storing a high resistance state or a low resistance state in a non-volatile manner, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate, wherein the variable resistance element includes: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 至少一个单元阵列形成在所述半导体衬底上方以具有可变电阻元件和存取元件的堆叠结构，所述可变电阻元件以非易失性方式存储高电阻状态或低电阻状态，所述存取元件具有在选择状态下为十倍以上的一定电压范围内的截止电阻值; 以及形成在所述半导体基板上的读/写电路，其中所述可变电阻元件包括：由包含至少一个过渡元件的复合化合物和用于容纳阳离子离子的空腔位置形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在其中的空腔位置的记录层。

75. 发明申请

US20070285963A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285963A1
公开(公告)日：2007-12-13
申请号：US11761282
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C5/02 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/147
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, each having memory cells, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed the word lines to the read/write circuit. The memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在衬底上，每个阵列具有存储单元，位线和字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 并且第三垂直布线将字线布置到读/写电路。存储单元包括用于存储作为信息的电阻值的可变电阻元件，电阻值具有由包含至少两种阳离子元素的复合化合物组成的记录层，至少一种类型的阳离子元素是具有“d “轨道，其中电子不完全填充，相邻阳离子元素之间的最短距离为0.32nm或更小。

76. 发明申请

US20070268750A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070268750A1
公开(公告)日：2007-11-22
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联连接在VRDEC和TG之间的PMOS晶体管P 2和高电压NMOS晶体管D 3; 在VRDEC和NA之间串联连接的PMOS晶体管P 1和高电压NMOS晶体管D 2; 串联在TG和Vss之间的NMOS晶体管N 2和高电压NMOS晶体管D 6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N 1和高电压NMOS晶体管D 5由解码输出Aa驱动。 P 1和P 2的闸门和排水沟交叉耦合。 D 3和D 2的门分别耦合到TG和NA。

77. 发明授权

US07158444B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07158444B2
公开(公告)日：2007-01-02
申请号：US11299758
申请日：2005-12-13
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C8/18
CPC分类号： G11C7/1036 , G11C7/1018 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.
摘要翻译：半导体存储器件包括存储单元阵列和控制电路。存储单元阵列具有以行和列排列的多个存储单元。存储单元存储数据，并根据地址信号进行选择。控制电路被配置为接收时钟信号和第一控制信号，并且在第一控制信号被断言之后响应于时钟信号输出多个数据。在第一控制信号置位之后，响应时钟信号的内部信号转换N次（N为正整数，大于或等于2），则数据的输出开始。在输出开始后的转换中输出至少一个数据。

78. 发明申请

US20060239073A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060239073A1
公开(公告)日：2006-10-26
申请号：US11389252
申请日：2006-03-27
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/0483 , G11C16/28 , G11C2211/5631 , G11C2211/5634
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M>2) physical quantity levels is written, and at least one reference cell, in which a reference physical quantity level is written, are defined in the memory cell array, and the sense amplifier circuit detects a cell current difference between the information cell and the reference cell selected simultaneously in the memory cell array to sense data defined by the M physical quantity levels of the information cell.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 以及读出放大器电路，被配置为读出存储单元阵列的数据，其中写入了M（M> 2）个物理量级别中的一个的多个信息单元和至少一个参考单元，其中在存储单元阵列中定义参考物理量电平，并且读出放大器电路检测在存储单元阵列中同时选择的信息单元和参考单元之间的单元电流差，以检测由M个物理量定义的数据信息单元的级别。

79. 发明申请

US20060209593A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060209593A1
公开(公告)日：2006-09-21
申请号：US11360536
申请日：2006-02-24
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5641
摘要： A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, and each pair cell is set to have different physical quantity levels in two memory cells therein, thereby storing M-value data defined by M=2n (where M>N and “n” is an integer equal to two or more), the M-value data being defined by such M combination states that differences of the physical quantity levels in the two memory cells are different from each other.
摘要翻译：半导体存储器件包括存储单元阵列，存储单元布置在其中，每个存储器单元可设置为具有多个物理量级别中的一个，同时选择构成用作数据存储单元的配对单元的两个存储器单元，其中每个存储单元是设置为N（其中N是等于三个或更多个的整数）物理量级别中的一个，并且每对单元被设置为在其中的两个存储器单元中具有不同的物理量级别，从而存储由M = （其中M> N和“n”是等于2或更大的整数），M值数据由这样的M组合定义，即两个物理量水平的差异存储单元彼此不同。

80. 发明申请

US20060197115A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20060197115A1
公开(公告)日：2006-09-07
申请号：US10551702
申请日：2003-04-03
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/768
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly connecting one ends of plural memory cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged along a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit.
摘要翻译：相变存储器件具有半导体衬底; 多个单元阵列，堆叠在半导体衬底之上，每个单元阵列具有以矩阵方式布置的存储单元，用于存储电阻值，作为通过存储单元的相变确定的数据，各通常连接多个存储单元的一端的位线沿着矩阵的第一方向布置，每个字线通常连接沿矩阵的第二方向布置的多个存储单元的另一端; 在半导体衬底上形成的用于读取和写入单元阵列数据的单元阵列的读/写电路; 布置在第一和第二边界之外的第一和第二垂直布线，其限定第一方向上的单元阵列的单元布局区域，以将各单元阵列的位线连接到读/写电路; 以及第三垂直布线，其布置在第三和第四边界之一之外，其限定第二方向上的单元布局区域，以将各单元阵列的字线连接到读/写电路。

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