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71. 发明授权

US07800217B2 Power semiconductor device connected in distinct layers of plastic 有权
标题翻译：功率半导体器件连接在不同的塑料层
公开(公告)号：US07800217B2
公开(公告)日：2010-09-21
申请号：US11746699
申请日：2007-05-10
申请人： Ralf Otremba , Helmut Strack
发明人： Ralf Otremba , Helmut Strack
IPC分类号： H01L23/12
CPC分类号： H01L23/5389 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/24 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/071 , H01L2224/06181 , H01L2224/24226 , H01L2224/32245 , H01L2224/371 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/83801 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2224/83855 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2224/8382 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.
摘要翻译：一种功率半导体器件及其制造方法。功率半导体器件具有至少一个功率半导体芯片，其在其顶侧和其后侧具有大面积电极。电极通过连接元件与外部触点电连接，功率半导体芯片和连接元件嵌入塑料封装中。该塑料包装具有多个塑料层，它们一个被压在另一个之上并具有平面平行的上侧。连接元件布置在至少一个平面平行的上侧，在塑料层之间压迫的层之间，作为图案化的金属层，并且通过接触通孔与外部触点电连接塑料层中的至少一层。

72. 发明申请

US20090230535A1 SEMICONDUCTOR MODULE 有权
标题翻译：半导体模块
公开(公告)号：US20090230535A1
公开(公告)日：2009-09-17
申请号：US12046680
申请日：2008-03-12
申请人： Ralf Otremba , Josef Hoeglauer , Helmut Strack , Xaver Schloegel
发明人： Ralf Otremba , Josef Hoeglauer , Helmut Strack , Xaver Schloegel
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3157 , H01L24/25 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2221/68345 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/2518 , H01L2224/73153 , H01L2224/76155 , H01L2224/82001 , H01L2224/82039 , H01L2224/82047 , H01L2224/82102 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1815 , H01L2224/82 , H01L2924/00
摘要： A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated.
摘要翻译：半导体模块。在一个实施例中，至少两个半导体芯片放置在载体上。然后用成型材料覆盖至少两个半导体芯片。提供至少两个半导体芯片的暴露部分。第一层导电材料施加在至少两个半导体芯片的暴露部分上，以电连接到至少两个半导体芯片的暴露部分上的接触焊盘。将至少两个半导体芯片分割。

73. 发明授权

US06670244B2 Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity 有权
公开(公告)号：US06670244B2
公开(公告)日：2003-12-30
申请号：US09943538
申请日：2001-08-30
申请人： Helmut Gassel , Werner Kanert , Helmut Strack , Franz Hirler , Herbert Pairitsch
发明人： Helmut Gassel , Werner Kanert , Helmut Strack , Franz Hirler , Herbert Pairitsch
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66333 , H01L29/66348 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.

74. 发明授权

US4903112A Semiconductor component with contact hole 失效
标题翻译：半导体元件带接触孔
公开(公告)号：US4903112A
公开(公告)日：1990-02-20
申请号：US212365
申请日：1988-06-22
申请人： Helmut Strack , Gottfried Schuh
发明人： Helmut Strack , Gottfried Schuh
IPC分类号： H01L29/78 , H01L21/285 , H01L21/331 , H01L21/336 , H01L23/485 , H01L29/08 , H01L29/41 , H01L29/73
CPC分类号： H01L29/0847 , H01L21/28531 , H01L23/485 , H01L2924/0002 , Y10S257/914
摘要： A semiconductor component. The semiconductor component has two superimposed semiconductor layers of different conduction materials. An upper layer is provided with an opening through which a lower layer is exposed. A space saving scheme for connecting electrically the two layers is provided, by depositing a connecting layer which contacts the upper layer at an edge only and the lower layer is contacted at its depth where its doping material maximum is located. This requires a doping equal to or greater than 10.sup.19 cm.sup.-3 for the upper layer, which is dependent on thickness.
摘要翻译：半导体元件。半导体元件具有不同导电材料的两个重叠的半导体层。上层设置有暴露下层的开口。通过沉积仅在边缘处接触上层的连接层，并且下层在其最大掺杂材料所在的深度处接触来提供用于连接两层电气的节省空间的方案。对于上层，这需要等于或大于1019cm-3的掺杂，其取决于厚度。

75. 发明授权

US4612448A Electronic switch 失效
标题翻译：电子开关
公开(公告)号：US4612448A
公开(公告)日：1986-09-16
申请号：US698000
申请日：1985-02-04
申请人： Helmut Strack
发明人： Helmut Strack
IPC分类号： H03K17/687 , H03K17/04 , H03K17/567 , H03K17/732 , H03K17/72
CPC分类号： H03K17/0406 , H03K17/567
摘要： Connected in series with a thyristor (1) are two IGFETs (2, 3) one to the anode side and the other to the cathode side. Between the inner thyristor zones (6, 8) and the outer IGFET connections, a threshold circuit (10, 11) is connected to each. The threshold voltage of the threshold circuit is higher than that of the p-n junctions between the outer and adjacent inner thyristor zones (6, 7; 8, 9) including the voltage drop of the conducting IGFET. The switch is turned off by operating to turn off the IGFETs. The current then flows via the threshold elements through the two inner zones (6, 8). The charge carriers of this diode are evacuated very quickly, since carrier injection from the outer zones is no longer possible.
摘要翻译：与晶闸管（1）串联连接的是两个IGFET（2,3），一个连接到阳极侧，另一个连接到阴极侧。在内部可控硅区域（6,8）和外部IGFET连接之间，连接有阈值电路（10,11）。阈值电路的阈值电压高于包括导电IGFET的电压降的外部和相邻的内部可控硅区域（6,7; 8,9）之间的p-n结的阈值电压。通过操作关闭开关即可关闭IGFET。电流然后通过两个内部区域（6,8）通过阈值元件流动。这种二极管的电荷载体被非常快地抽真空，因为从外部区域的载流子注入是不可能的。

76. 发明授权

US4543596A Insulated-gate field-effect transistor (IGFET) with injector zone 失效
标题翻译：具有注入区的绝缘栅场效应晶体管（IGFET）
公开(公告)号：US4543596A
公开(公告)日：1985-09-24
申请号：US510081
申请日：1983-06-30
申请人： Helmut Strack , Jeno Tihanyi
发明人： Helmut Strack , Jeno Tihanyi
IPC分类号： H01L29/78 , H01L21/331 , H01L29/10 , H01L29/73 , H01L29/739 , H01L27/02
CPC分类号： H01L29/1095 , H01L29/7393 , H01L29/7803
摘要： An IGFET assembly, includes a semiconductor substrate of a given first conductivity type having first and second surfaces, an IGFET having at least one channel zone of a second conductivity type opposite the first given conductivity type embedded in the first surface of the substrate, a source zone of the first conductivity type embedded planar in the channel zone, a drain zone adjacent the first surface of the substrate, a drain electrode connected to the second surface of the substrate, an insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, a contact for connecting the injector zone to a voltage source, an emitter zone of the first conductivity type embedded in the injector zone, the emitter zone having a heavier doping than the injector zone, the injector zone including a part thereof emerging to the first surface of the substrate, the drain zone having a part thereof emerging to the first surface of the substrate between the channel zone and the injector zone, the parts of the injector and drain zones emerging to the first surface of the substrate being covered by the gate electrode, and the injector zone having a surface and having a doping, at least at the surface thereof, forming a channel in the surface of the injector zone connecting the drain zone to the emitter zone when a voltage is present switching the IGFET into conduction.
摘要翻译： IGFET组件包括具有第一和第二表面的给定第一导电类型的半导体衬底，具有至少一个第二导电类型的沟道区的IGFET，所述第二导电类型与嵌入衬底的第一表面中的第一给定导电类型相反，源极在沟道区中嵌入平面的第一导电类型的区域，与衬底的第一表面相邻的漏极区域，连接到衬底的第二表面的漏极电极，至少设置在衬底的第一表面上的绝缘层设置在所述绝缘层上的一个栅电极，嵌入在所述基板的第一表面中的至少一个第二导电类型的注入区，用于将所述注入区连接到电压源的接触点，所述第一导电类型的发射极区嵌入喷射器区域，发射区具有比喷射器区域更重的掺杂，喷射器区域包括其出现到冷杉的部分衬底的表面，排水区具有其一部分在通道区域和喷射器区域之间出现在衬底的第一表面上，出射到衬底的第一表面的喷射器和排出区域的部分被栅电极和具有表面并且具有掺杂的注入器区域，至少在其表面处，当存在电压切换IGFET导通时，在连接漏区与发射区的喷射器区域的表面中形成通道。

77. 发明申请

US20100297810A1 Power Semiconductor Device and Method for Its Production 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20100297810A1
公开(公告)日：2010-11-25
申请号：US12850902
申请日：2010-08-05
申请人： Ralf Otremba , Helmut Strack
发明人： Ralf Otremba , Helmut Strack
IPC分类号： H01L21/50
CPC分类号： H01L23/5389 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/24 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/071 , H01L2224/06181 , H01L2224/24226 , H01L2224/32245 , H01L2224/371 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/83801 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2224/83855 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2224/8382 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.
摘要翻译：一种功率半导体器件及其制造方法。功率半导体器件具有至少一个功率半导体芯片，其在其顶侧和其后侧具有大面积电极。电极通过连接元件与外部触点电连接，功率半导体芯片和连接元件嵌入塑料封装中。该塑料包装具有多个塑料层，它们一个被压在另一个之上并具有平面平行的上侧。连接元件布置在至少一个平面平行的上侧，在塑料层之间压迫的层之间，作为图案化的金属层，并且通过接触通孔与外部触点电连接塑料层中的至少一层。

78. 发明申请

US20070284720A1 Power semiconductor device and method for its production 有权
标题翻译：功率半导体器件及其生产方法
公开(公告)号：US20070284720A1
公开(公告)日：2007-12-13
申请号：US11746699
申请日：2007-05-10
申请人： Ralf Otremba , Helmut Strack
发明人： Ralf Otremba , Helmut Strack
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/24 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/071 , H01L2224/06181 , H01L2224/24226 , H01L2224/32245 , H01L2224/371 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/83801 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2224/83855 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2224/8382 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.
摘要翻译：一种功率半导体器件及其制造方法。功率半导体器件具有至少一个功率半导体芯片，其在其顶侧和其后侧具有大面积电极。电极通过连接元件与外部触点电连接，功率半导体芯片和连接元件嵌入塑料封装中。该塑料包装具有多个塑料层，它们一个被压在另一个之上并具有平面平行的上侧。连接元件布置在至少一个平面平行的上侧，在塑料层之间压迫的层之间，作为图案化的金属层，并且通过接触通孔与外部触点电连接塑料层中的至少一层。

79. 发明授权

US6072220A Integrated resistor 失效
标题翻译：集成电阻
公开(公告)号：US6072220A
公开(公告)日：2000-06-06
申请号：US206577
申请日：1998-12-07
申请人： Helmut Strack
发明人： Helmut Strack
IPC分类号： H01L27/04 , H01L21/02 , H01L21/22 , H01L21/822 , H01L27/02 , H01L29/8605
CPC分类号： H01L28/20 , H01L29/8605 , Y10S257/904
摘要： A semiconductor body includes a lightly doped semiconductor zone of a second conductivity type. A first oxide layer is produced on the semiconductor body. A structured polysilicon layer is produced on the oxide layer. The polysilicon layer acts as a mask so that the dopants of one conductivity type are implanted and driven into the surface of the semiconductor zone. A second oxide layer is then produced on the surface of the polysilicon layer and the semiconductor zone. A spacer is etched from this oxide layer. Dopants of the second conductivity type are implanted and driven into the surface of the semiconductor zone. A narrow resistor zone remains lying under the polysilicon layer.
摘要翻译：半导体本体包括第二导电类型的轻掺杂半导体区。在半导体本体上产生第一氧化物层。在氧化物层上产生结构化的多晶硅层。多晶硅层用作掩模，使得一种导电类型的掺杂剂被注入并驱动到半导体区的表面中。然后在多晶硅层和半导体区域的表面上产生第二氧化物层。从该氧化物层蚀刻间隔物。将第二导电类型的掺杂剂注入并驱动到半导体区域的表面中。窄电阻区域仍然位于多晶硅层下面。

80. 发明授权

US06063684A Method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers 失效
标题翻译：从坩埚拉制的硅片上消除残余氧污染的方法
公开(公告)号：US06063684A
公开(公告)日：2000-05-16
申请号：US146967
申请日：1998-09-04
申请人： Helmut Strack
发明人： Helmut Strack
IPC分类号： C30B33/00 , H01L21/322 , H01C21/76
CPC分类号： C30B29/06 , C30B33/00 , H01L21/3225
摘要： In a method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers, a number of trenches are etched into the front side of a crucible-drawn silicon wafer and that the silicon wafer is subsequently tempered at approximately 1100.degree. C. As a result of the extremely large surface area in the front side of the silicon wafer, oxygen contaminants can effectively diffuse out. After the oxygen drive-out has ensued, the trenches are filled bubble-free with epitaxially deposited silicon and the active structures are processed into the front side.
摘要翻译：在从坩埚拉制的硅晶片中消除残余氧污染的方法中，将许多沟槽蚀刻到坩埚拉制的硅晶片的前侧，并且随后在大约1100℃下回火硅晶片。结果是硅晶片正面的极大表面积，氧气污染物可以有效地扩散出去。在发生氧气驱出之后，通过外延沉积的硅将沟槽充满无气泡，并将活性结构加工成正面。

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