专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20110225473A1 READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING 有权
标题翻译：阅读操作非易失存储与补偿的联系
公开(公告)号：US20110225473A1
公开(公告)日：2011-09-15
申请号：US13113312
申请日：2011-05-23
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C29/52 , G11C16/04 , G11C16/26 , G06F11/07
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。

72. 发明授权

US07971127B2 Guided simulated annealing in non-volatile memory error correction control 有权
标题翻译：引导模拟退火在非易失性存储器中的纠错控制
公开(公告)号：US07971127B2
公开(公告)日：2011-06-28
申请号：US11694951
申请日：2007-03-31
申请人： Henry Chin , Nima Mokhlesi
发明人： Henry Chin , Nima Mokhlesi
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： G11C11/5642 , G06F11/1072 , G11C29/00
摘要： Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.
摘要翻译：使用迭代概率解码对非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。可以使用基于数据中的误差水平的可调节温度参数进行模拟退火。模拟退火可以将随机性作为噪声引入到解码过程中。此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。引入一定程度的随机性增加了灵活性，允许在数据可能不可纠正的情况下可能更快的收敛时间和收敛。

73. 发明申请

US20110111583A1 METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY 有权
标题翻译：降低非易失性存储器中浮动栅之间耦合的方法
公开(公告)号：US20110111583A1
公开(公告)日：2011-05-12
申请号：US13010563
申请日：2011-01-20
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

74. 发明授权

US07911838B2 Read operation for non-volatile storage with compensation for coupling 有权
标题翻译：对非易失性存储进行读操作，对耦合进行补偿
公开(公告)号：US07911838B2
公开(公告)日：2011-03-22
申请号：US12622966
申请日：2009-11-20
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。

75. 发明申请

US20110026353A1 DATA REFRESH FOR NON-VOLATILE STORAGE 有权
标题翻译：数据刷新非易失性存储
公开(公告)号：US20110026353A1
公开(公告)日：2011-02-03
申请号：US12903067
申请日：2010-10-12
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/3431
摘要： Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element.
摘要翻译：公开了用于在非易失性存储设备中刷新数据的技术，其足以抵抗错误或损坏的数据位，但不会频繁地干扰存储器访问或者对存储器单元造成过度的应力。一个实施例包括确定基于第一组中的数据的条件来执行存储在设备中的第一组非易失性存储元件中的数据的刷新，确定设备中的第二组非易失性存储元件应该基于当第二组非易失性存储元件被最后编程为相对于第一组非易失性存储元件最后被编程的时间的时间来执行刷新过程，并且对第二组非易失性存储元件执行刷新过程。

76. 发明授权

US07851851B2 Three dimensional NAND memory 有权
标题翻译：三维NAND存储器
公开(公告)号：US07851851B2
公开(公告)日：2010-12-14
申请号：US11691939
申请日：2007-03-27
申请人： Nima Mokhlesi , Roy Scheuerlein
发明人： Nima Mokhlesi , Roy Scheuerlein
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.
摘要翻译：单片三维NAND串包括位于第二存储单元上的第一存储单元。外部在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区，使得在第一存储单元的半导体有源区和第二存储单元的半导体有源区之间存在限定的边界。

77. 发明授权

US07808831B2 Read disturb mitigation in non-volatile memory 有权
标题翻译：在非易失性存储器中读取干扰减轻
公开(公告)号：US07808831B2
公开(公告)日：2010-10-05
申请号：US12165302
申请日：2008-06-30
申请人： Nima Mokhlesi , Klaus Schuegraf
发明人： Nima Mokhlesi , Klaus Schuegraf
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/3418 , G11C16/3427 , G11C29/00
摘要： Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.
摘要翻译：非易失性存储器中的读取干扰减少。在一个方面，当从主机接收到用于读取所选择的字线的读取命令时，随机选择未被选择用于读取的字线，并且感测其存储元件以确定用于读取所选字线的优化读取比较电平。或者，可以基于在读取所选字线的存储元件中获得的纠错度量，针对整个块指示刷新操作。特别是当所选字线被重复选择用于读取时，这是有用的，将其它字线暴露于额外的读取干扰。在另一方面，当存储多个数据状态时，通过例如来自阈值电压分布的感测获得一个读取比较电平，并且从公式导出其它读取的比较电平。

78. 发明授权

US07808038B2 Method of making three dimensional NAND memory 有权
标题翻译：制作三维NAND存储器的方法
公开(公告)号：US07808038B2
公开(公告)日：2010-10-05
申请号：US11691858
申请日：2007-03-27
申请人： Nima Mokhlesi , Roy Scheuerlein
发明人： Nima Mokhlesi , Roy Scheuerlein
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.
摘要翻译：单片三维NAND串包括位于第二存储单元上的第一存储单元。第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体地区。第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

79. 发明申请

US20100202207A1 ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY 有权
公开(公告)号：US20100202207A1
公开(公告)日：2010-08-12
申请号：US12767660
申请日：2010-04-26
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C7/02 , G11C11/5635 , G11C11/5642 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C2211/5621
摘要： Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.

80. 发明授权

US07755132B2 Nonvolatile memories with shaped floating gates 有权
标题翻译：具有形状浮动门的非易失性存储器
公开(公告)号：US07755132B2
公开(公告)日：2010-07-13
申请号：US11465025
申请日：2006-08-16
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： H01L29/788 , H01L21/8247
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different patterns to obtain floating gates of different orientations.
摘要翻译：在使用浮动门来存储电荷的非易失性存储器中，各个浮动门是L形的。 L形浮栅的方向可以在位线方向上交替，并且也可以在字线方向上交替。通过使用不同图案的蚀刻掩模蚀刻导电部分来形成L形浮栅，以获得不同取向的浮动栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式